參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 26/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
120 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.7.5 DMA Interrupt Reason register
This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a
DMA command is executed. An interrupt source is cleared by writing logic 1 to the
corresponding bit. On detecting the interrupt, the external microprocessor must read the
DMA Interrupt Reason register and mask it with the corresponding bits in the DMA
Interrupt Enable register to determine the source of the interrupt.
The bit allocation is given in Table 133.
[1]
The reserved bits should always be written with the reset value.
Table 132. DMA Hardware register (address 023Ch) bit description
Bit
Symbol
Description
7 to 4
-
reserved
3
DACK_POL
DACK Polarity: Selects the DMA acknowledgment polarity.
0 — DACK is active LOW
1 — DACK is active HIGH
2
DREQ_POL
DREQ Polarity: Selects the DMA request polarity.
0 — DREQ is active LOW
1 — DREQ is active HIGH
1 to 0
-
reserved
Table 133. DMA Interrupt Reason register (address 0250h) bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
GDMA_
STOP
reserved
INT_EOT
reserved[1]
DMA_
XFER_OK
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
Reset
00000000
Bus reset
00000000
Access
R/W
Table 134. DMA Interrupt Reason register (address 0250h) bit description
Bit
Symbol
Description
15 to 13
-
reserved
12
GDMA_STOP
GDMA Stop: When the GDMA_STOP command is issued to DMA
Command registers, it means that the DMA transfer has
successfully terminated.
11
-
reserved
10
INT_EOT
Internal EOT: Logic 1 indicates that an internal EOT is detected;
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