參數資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數: 18/164頁
文件大小: 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
113 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is
programmed as 64 bytes, the Buffer Length register should be lled with 62 bytes just
before the microcontroller writes the last packet of 62 bytes. This ensures that the last
packet, which is a short packet of 62 bytes, is automatically validated.
Use the VENDP bit in the Control register if you are not using the Buffer Length register.
This is applicable only to PIO mode access.
OUT endpoint: The DATACOUNT value is automatically initialized to the number of data
bytes sent by the host on each ACK.
Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is
output as the lower byte (LSByte).
10.6.5 DcBufferStatus register
This register is accessed using an index. The endpoint index must rst be set before
accessing this register for the corresponding endpoint. It reects the status of the endpoint
FIFO. Table 117 shows the bit allocation of the DcBufferStatus register.
Remark: This register is not applicable to the control endpoint.
Remark: For the endpoint IN data transfer, rmware must ensure a 200 ns delay between
writing of the data packet and reading the DcBufferStatus register. For the endpoint OUT
data transfer, rmware must also ensure a 200 ns delay between the reception of the
endpoint interrupt and reading the DcBufferStatus register. For more information, refer to
[1]
The reserved bits should always be written with the reset value.
Table 116. Buffer Length register (address 021Ch) bit description
Bit
Symbol
Access
Value
Description
15 to 0 DATACOUNT
[15:0]
R/W
0000h
Data Count: Determines the current packet size of the indexed endpoint
FIFO.
Table 117. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
BUF1
BUF0
Reset
00000000
Bus reset
00000000
Access
R/W
R
Table 118. DcBufferStatus - Device Controller Buffer Status register (address 021Eh) bit
description
Bit
Symbol
Description
7 to 2
-
reserved
1 to 0
BUF[1:0]
Buffer:
00 — The buffers are not lled.
01 — One of the buffers is lled.
10 — One of the buffers is lled.
11 — Both the buffers are lled.
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