參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 100/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
39 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Specication for
8.2.6 PORTSC1 register
The Port Status and Control (PORTSC) register (bit allocation: Table 23) is in the power
well. It is reset by hardware only when the auxiliary power is initially applied or in response
to a host controller reset. The initial conditions of a port are:
No peripheral connected
Port disabled
If the port has power control, software cannot change the state of the port until it sets port
power bits. Software must not attempt to change the state of the port until the power is
stable on the port (maximum delay is 20 ms from the transition).
[1]
The reserved bits should always be written with the reset value.
Table 22.
CONFIGFLAG - Congure Flag register (address 0060h) bit description
Bit
Symbol Description[1]
31 to 1 -
reserved
0CF
Congure Flag: The host software sets this bit as the last action when it is
conguring the host controller. This bit controls the default port-routing control
logic.
Table 23.
PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
PTC[3:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
PIC[1:0]
PO
PP
LS[1:0]
reserved[1]
PR
Reset
00100000
Access
R
R/W
R
Bit
7
6
5
4
3
2
1
0
Symbol
SUSP
FPR
reserved[1]
PED
ECSC
ECCS
Reset
00000000
Access
R/W
R
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