參數(shù)資料
型號(hào): ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 31/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
125 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.8.2 DcChipID register
This read-only register contains the chip identication and hardware version numbers.
The rmware must check this information to determine functions and features supported.
The register contains 3 bytes, and the bit allocation is shown in Table 143.
10.8.3 Frame Number register
This read-only register contains the frame number of the last successfully received
Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in
10.8.4 DcScratch register
This 16-bit register can be used by the rmware to save and restore information. For
example, the device status before it enters the suspend state; see Table 146.
2
PSOF
Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or
SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125
s period) that is not
synchronized to the USB bus SOF or
SOF.
1
SOF
SOF interrupt: Logic 1 indicates that a SOF or
SOF was received.
0
BRESET
Bus Reset: Logic 1 indicates that a USB bus reset was detected.
Table 142. DcInterrupt - Device Controller Interrupt register (address 0218h) bit
description …continued
Bit
Symbol
Description
Table 143. DcChipID - Device Controller Chip Identier register (address 0270h) bit description
Bit
Symbol
Access
Value
Description
31 to 0
CHIPID[31:0]
R
0015 8210h Chip ID: This registers represents the hardware version number
(0015h) and the chip ID (8210h) for the peripheral controller.
Table 144. Frame Number register (address 0274h) bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
MICROSOF[2:0]
SOFR[10:8]
Reset
00000000
Bus reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
SOFR[7:0]
Reset
00000000
Bus reset
00000000
Access
RRRRRRRR
Table 145. Frame Number register (address 0274h) bit description
Bit
Symbol
Description
15 to 14
-
reserved
13 to 11
MICROSOF[2:0]
microframe number
10 to 0
SOFR[10:0]
frame number
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