參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 115/164頁
文件大?。?/td> 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
53 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
[1]
For a 32-bit operation, the default wake-up counter value is 10
s. For a 16-bit operation, the wake-up
counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
8.4 Interrupt registers
8.4.1 HcInterrupt register
The bits of this register indicate the interrupt source, dening the events that determined
the INT generation. Clearing the bits that were set because of the events listed is done by
writing back logic 1 to the respective position. All bits must be reset before enabling new
interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN
in the HW Mode Control register. Table 53 shows the bit allocation of the HcInterrupt
register.
2
OC2_PWR
OC2_N Powered: Controls the powering of the overcurrent detection
circuitry for port 2.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
1
OC1_PWR
OC1_N Powered: Controls the powering of the overcurrent detection
circuitry for port 1.
0 — Overcurrent detection is powered on or enabled during suspend.
1 — Overcurrent detection is powered off or disabled during suspend.
This may be useful when connecting a faulty device while the system
is in standby.
0
HC_CLK_
EN
Host Controller Clock Enabled: Controls internal clocks during
suspend.
0 — Clocks are disabled during suspend. This is the default value.
Only the LazyClock of 100 kHz
± 40 % will be left running in suspend if
this bit is logic 0. If clocks are stopped during suspend, CLKREADY
IRQ will be generated when all clocks are running stable.
1 — All clocks are enabled even in suspend.
Table 52.
Power Down Control register (address 0354h) bit description …continued
Bit[1]
Symbol
Description
Table 53.
HcInterrupt - Host Controller Interrupt register (address 0310h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
OTG_IRQ
ISO_IRQ
ATL_IRQ
Reset
00000000
Access
R/W
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