參數(shù)資料
型號： ISP1761ET,518
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝： 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù)： 120/164頁
文件大小： 767K
代理商： ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
58 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
8.4.6 ISO IRQ MASK AND register
Each bit of this register corresponds to one of the 32 ISO PTDs dened, and is a
hardware IRQ mask for each PTD done map. For details, see Section 7.4.
Table 60 provides the bit description of the register.
8.4.7 INT IRQ MASK AND register
Each bit of this register (see Table 61) corresponds to one of the 32 INT PTDs dened,
and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.
8.4.8 ATL IRQ MASK AND register
Each bit of this register corresponds to one of the 32 ATL PTDs dened, and is a
hardware IRQ mask for each PTD done map. For details, see Section 7.4.
Table 62 shows the bit description of the register.
8.5 Philips Transfer Descriptor (PTD)
The standard EHCI data structures as described in Ref. 2 “Enhanced Host Controller
operation that is managed by the hardware state machine.
Table 59.
ATL IRQ Mask OR register (address 0320h) bit description
Bit
Symbol
Access
Value
Description
31 to 0
ATL_IRQ_MASK_
OR[31:0]
R/W
0000 0000h
ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition dened between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
dene a certain OR condition.
Table 60.
ISO IRQ Mask AND register (address 0324h) bit description
Bit
Symbol
Access
Value
Description
31 to 0
ISO_IRQ_MASK_
AND[31:0]
R/W
0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.
0 — No AND condition dened between ISO PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
dene a certain AND condition between the 32 INT PTDs.
Table 61.
INT IRQ MASK AND register (address 0328h) bit description
Bit
Symbol
Access
Value
Description
31 to 0
INT_IRQ_MASK_
AND[31:0]
R/W
0000 0000h
INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.
0 — No OR condition dened between INT PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
dene a certain AND condition between the 32 INT PTDs.
Table 62.
ATL IRQ MASK AND register (address 032Ch) bit description
Bit
Symbol
Access
Value
Description
31 to 0
ATL_IRQ_
MASK_AND
[31:0]
R/W
0000 0000h
ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.
0 — No OR condition dened between ATL PTDs.
1 — The bits corresponding to certain PTDs are set to logic 1 to
dene a certain AND condition between the 32 ATL PTDs.
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