參數(shù)資料
型號: ISP1761ET,518
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA128
封裝: 9 X 9 MM, 0.80 MM HEIGHT, PLASTIC, MO-195, SOT857-1, TFBGA-128
文件頁數(shù): 29/164頁
文件大小: 767K
代理商: ISP1761ET,518
ISP1761_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 13 March 2008
123 of 163
NXP Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.8 General registers
10.8.1 DcInterrupt register
The DcInterrupt register consists of 4 bytes. The bit allocation is given in Table 141.
When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the DcInterrupt register content is non-zero, the INT output
will be asserted. On detecting the interrupt, the external microprocessor must read the
DcInterrupt register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller has only one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register.
Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can
be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt
Reason register and writing logic 1 to the DMA bit of the DcInterrupt register.
Table 140. DMA Burst Counter register (address 0264h) bit description
Bit
Symbol
Description
15 to 13
-
reserved
12 to 0
BURST
COUNTER[12:0]
Burst Counter: This register denes the burst length. The counter
must be programmed to be a multiple of two in 16-bit mode and four
in 32-bit mode.
The value of the burst counter must be programmed so that the
buffer counter is a factor of the burst counter. In 16-bit mode, DREQ
will drop at every DMA read or write cycle when the burst counter
equals 2. In 32-bit mode, DREQ will drop at every DMA read or
write cycle when the burst counter equals 4.
Table 141. DcInterrupt - Device Controller Interrupt register (address 0218h) bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
EP7TX
EP7RX
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
EP6TX
EP6RX
EP5TX
EP5RX
EP4TX
EP4RX
EP3TX
EP3RX
Reset
00000000
Bus reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
EP2TX
EP2RX
EP1TX
EP1RX
EP0TX
EP0RX
reserved[1]
EP0SETUP
Reset
000000
00
Bus reset
000000
00
Access
R/W
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