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參數(shù)資料
| 型號： | ISP1583ET1,118 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64 |
| 文件頁數(shù)： | 9/100頁 |
| 文件大?。?/td> | 508K |
| 代理商： | ISP1583ET1,118 |
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ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
15 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
The ISP1583 is a device that can initiate SRP.
8.6 NXP high-speed transceiver
8.6.1 NXP Parallel Interface Engine (PIE)
In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel
bidirectional data interface. The functions of the HS module also include bit-stufng or
de-stufng and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.
8.6.2 Peripheral circuit
To maintain a constant current driver for HS transmit circuits and to bias other analog
circuits, an internal band gap reference circuit and an RREF resistor form the reference
current. This circuit requires an external precision resistor (12.0 k
± 1 %) connected to
the analog ground.
8.6.3 HS detection
The ISP1583 handles more than one electrical state, Full-Speed (FS) or High-Speed
(HS), under the USB specication. When the USB cable is connected from the peripheral
to the host controller, the ISP1583 defaults to the FS state, until it sees a bus reset from
the host controller.
During the bus reset, the peripheral initiates an HS chirp to detect whether the host
controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there
is an HS host connected, then the ISP1583 switches to the HS state.
In the HS state, the ISP1583 must observe the bus for periodic activity. If the bus remains
inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero
(SE0) condition on the USB bus. If an SE0 condition is detected for the designated time
(100
s to 875 s; refer to Ref. 1 “Universal Serial Bus Specication Rev. 2.0”,
Section 7.1.7.6), the ISP1583 switches to the HS chirp state to perform an HS detection
handshake. Otherwise, the ISP1583 remains in the FS state, adhering to the bus-suspend
specication.
8.6.4 Isolation
Ensure that the DP and DM lines are maintained in a clean state, without any residual
voltage or glitches. Once the ISP1583 is reset and the clock is available, ensure that there
are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines.
Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1583
DP and DM lines, there is a possibility of the ISP1583 clocking this state into the internal
core, causing unknown behaviors.
8.7 NXP Serial Interface Engine (SIE)
The NXP SIE implements the full USB protocol layer. It is completely hardwired for speed
and needs no rmware intervention. The functions of this block include: synchronization
pattern recognition, parallel or serial conversion, bit-stufng or de-stufng, CRC checking
or generation, Packet IDentier (PID) verication or generation, address recognition,
handshake evaluation or generation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1583ET1-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET1TM | 制造商:STMicroelectronics 功能描述: |
| ISP1583ET2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller |
| ISP1583ET2,518 | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET2-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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