- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67723 > ISP1583ET1,118 (ST-ERICSSON) UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 PDF資料下載
參數(shù)資料
| 型號： | ISP1583ET1,118 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64 |
| 文件頁數(shù)： | 58/100頁 |
| 文件大?。?/td> | 508K |
| 代理商： | ISP1583ET1,118 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
59 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.4.10 DMA Burst Counter register (address: 64h)
Table 80 shows the bit allocation of the 2-byte register.
9.5 General registers
9.5.1 Interrupt register (address: 18h)
The Interrupt register consists of 4 bytes. The bit allocation is given in Table 82.
When a bit is set in the Interrupt register, it indicates that the hardware condition for an
interrupt has occurred. When the Interrupt register content is nonzero, the INT output will
be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the
external microprocessor must read the Interrupt register and mask it with the
corresponding bits in the Interrupt Enable register to determine the source of the interrupt.
Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various
bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.
The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in
the DMA Interrupt Reason register (see Table 72 and Table 73).
Fig 17. Programmable strobe timing
x
(N + 1) cycles
004aaa125
Table 80.
DMA Burst Counter register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
BURSTCOUNTER[12:8]
Reset
-
00000
Bus reset
-
00000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
BURSTCOUNTER[7:0]
Reset
00000010
Bus reset
00000010
Access
R/W
Table 81.
DMA Burst Counter register: bit description
Bit
Symbol
Description
15 to 13
-
reserved
12 to 0
BURSTCOUNTER
[12:0]
Burst Counter: This register denes the burst length. The
counter must be programmed to be a multiple of two in 16-bit
mode. The value of the burst counter must be programmed so
that the burst counter is a factor of the buffer size.
It is used to determine the assertion and deassertion of DREQ.
相關PDF資料 |
PDF描述 |
|---|---|
| ISP1583BS,551 | UNIVERSAL SERIAL BUS CONTROLLER, PQCC64 |
| ISP1583ET2 | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| ISP1761ET,518 | UNIVERSAL SERIAL BUS CONTROLLER, PBGA128 |
| ISP1761BE,518 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| ISP1761BE,551 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1583ET1-T | 功能描述:外圍驅動器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET1TM | 制造商:STMicroelectronics 功能描述: |
| ISP1583ET2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller |
| ISP1583ET2,518 | 功能描述:外圍驅動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET2-T | 功能描述:外圍驅動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。