參數資料
型號： ISP1583ET1,118
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝： 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁數： 10/100頁
文件大小： 508K
代理商： ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
16 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
8.8 SoftConnect
The USB connection is established by pulling pin DP (for full-speed devices) to HIGH
through a 1.5 k
pull-up resistor. In the ISP1583, an external 1.5 k pull-up resistor must
be connected between pin RPU and 3.3 V. The RPU pin connects the pull-up resistor to
pin DP, when bit SOFTCT in the Mode register is set (see Table 24 and Table 25). After a
hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0). The USB
bus reset does not change the value of bit SOFTCT.
When VBUS is not present, the SOFTCT bit must be set to logic 0 to comply with the
back-drive voltage.
8.9 Reconguring endpoints
The ISP1583 endpoints have a limitation when implementing a composite device with at
least two functionalities that require the support of alternate settings, for example, the
video class and audio class devices. The ISP1583 endpoints cannot be recongured on
the y because it is implemented as a FIFO base. The internal RAM partition will be
corrupted if there is a need to recongure endpoints on the y because of alternate
settings request, causing data corruption.
For details and work-around, refer to Ref. 3 “Using ISP1582/3 in a composite device
8.10 System controller
The system controller implements the USB power-down capabilities of the ISP1583.
Registers are protected against data corruption during wake-up following a resume (from
the suspend state) by locking the write access, until an unlock code is written to the
Unlock Device register (see Table 90 and Table 91).
8.11 Modes of operation
The ISP1583 has two bus conguration modes, selected using pin BUS_CONF/DA0 at
power-up:
Split bus mode (BUS_CONF/DA0 = LOW): 8-bit multiplexed address and data bus,
and separate 8-bit or 16-bit DMA bus
Generic processor mode (BUS_CONF/DA0 = HIGH): separate 8-bit address and
16-bit data bus
Details of bus congurations for each mode are given in Table 5. Typical interface circuits
for each mode are given in Section 14.
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相關代理商/技術參數
參數描述
ISP1583ET1-T 功能描述:外圍驅動器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET1TM 制造商:STMicroelectronics 功能描述:
ISP1583ET2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller
ISP1583ET2,518 功能描述:外圍驅動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1583ET2-T 功能描述:外圍驅動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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