參數(shù)資料
型號: ISP1583ET1,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁數(shù): 50/100頁
文件大?。?/td> 508K
代理商: ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
52 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
[2]
PIO read or write that started using the DMA Command register only performs 16-bit transfer.
9.4.4 DMA Hardware register (address: 3Ch)
The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 58.
This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and
DIOW) and DMA mode (master or slave). It also controls whether the upper and lower
parts of the data bus are swapped (bits ENDIAN[1:0]), for modes GDMA (slave) and
MDMA (master) only.
Table 58.
DMA Hardware register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
ENDIAN[1:0]
EOT_POL
MASTER
ACK_POL
DREQ_
POL
WRITE_
POL
READ_
POL
Reset
00000100
Bus reset
00000100
Access
R/W
Table 59.
DMA Hardware register: bit description
Bit
Symbol
Description
7 to 6
ENDIAN[1:0]
Endian: These bits determine whether the data bus is swapped between
the internal RAM and the DMA bus. This only applies for modes GDMA
(slave) and MDMA (master).
00 — Normal data representation; 16-bit bus: MSByte on DATA[15:8] and
LSByte on DATA[7:0].
01 — Swapped data representation; 16-bit bus: MSByte on DATA[7:0] and
LSByte on DATA[15:8].
10 — reserved
11 — reserved
Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must
always be set to logic 00.
5
EOT_POL
EOT Polarity: Selects the polarity of the End-Of-Transfer input; used in
GDMA slave mode only.
0 — EOT is active LOW
1 — EOT is active HIGH
4
MASTER
Master or Slave Selection: Selects DMA master or slave mode.
0 — GDMA slave mode
1 — MDMA master mode
3
ACK_POL
Acknowledgment Polarity: Selects the DMA acknowledgment polarity.
0 — DACK is active LOW
1 — DACK is active HIGH
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