參數(shù)資料
型號(hào): ISP1583ET1,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁(yè)數(shù): 42/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
45 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.4 DMA registers
Two types of Generic DMA transfers and three types of IDE-specied transfers can be
done by writing the proper opcode in the DMA Command register.
Control bits are given in Table 49 (Generic DMA transfers) and Table 50 (IDE-specied
transfers).
GDMA read/write (opcode = 00h/01h) — Generic DMA slave mode. Depending on the
MODE[1:0] bits set in the DMA Conguration register, the DACK, DIOR or DIOW signal
strobes data. These signals are driven by the external DMA controller.
GDMA slave mode can operate in either counter mode or EOT-only mode.
In counter mode, bit DIS_XFER_CNT in the DMA Conguration register must be set to
logic 0. The DMA Transfer Counter register must be programmed before any DMA
command is issued. The DMA transfer counter is set by writing from the LSByte to the
MSByte (address: 34h to 37h). The DMA transfer count is internally updated only after the
MSByte is written. Once the DMA transfer is started, the transfer counter starts
decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated
by the ISP1583. If the DMA master wishes to terminate the DMA transfer, it can issue an
EOT signal to the ISP1583. This EOT signal overrides the transfer counter and can
terminate the DMA transfer at any time.
Table 48.
Endpoint Type register: bit description
Bit
Symbol
Description
15 to 5
-
reserved
4
NOEMPKT
No Empty Packet: Logic 0 causes the ISP1583 to return a null length
packet for the IN token after the DMA IN transfer is complete. For ATA
mode or the DMA IN transfer, which does not require a null length
packet after DMA completion, set to logic 1 to disable the generation of
the null length packet.
3
ENABLE
Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.
The memory size is allocated as specied in the Endpoint
MaxPacketSize register. Logic 0 disables the FIFO.
Remark: Stalling a data endpoint will confuse the Data Toggle bit on the
stalled endpoint because the internal logic picks up from where it has
stalled. Therefore, the Data Toggle bit must be reset by disabling and
re-enabling the corresponding endpoint (by setting bit ENABLE to
logic 0, followed by logic 1 in the Endpoint Type register) to reset the
PID.
2
DBLBUF
Double Buffering: Logic 1 enables double buffering for the indexed
endpoint. Logic 0 disables double buffering.
Remark: When performing a write to two empty buffers, ensure that a
minimum of 200 ns delay is provided from the last write of the rst buffer
to the rst write of the second buffer. Otherwise, the rst few data bytes
may not be written to the second buffer, causing data corruption.
1 to 0
ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type.
00 — not used
01 — Isochronous
10 — Bulk
11 — Interrupt
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