參數(shù)資料
型號(hào): ISP1583ET1,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁(yè)數(shù): 40/100頁(yè)
文件大?。?/td> 508K
代理商: ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
43 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Table 43 shows the bit allocation of the Buffer Status register.
9.3.6 Endpoint MaxPacketSize register (address: 04h)
This register determines the maximum packet size for all endpoints, except set-up token
buffer, control IN and control OUT. The register contains 2 bytes, and the bit allocation is
given in Table 45.
Each time the register is written, the Buffer Length register of the corresponding endpoint
is re-initialized to the FFOSZ eld value. Bits NTRANS control the number of transactions
allowed in a single microframe (for high-speed isochronous and interrupt endpoints only).
Table 43.
Buffer Status register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
BUF1
BUF0
Reset
------
0
Bus reset
------
0
Access
------
R
Table 44.
Buffer Status register: bit description
Bit
Symbol
Description
7 to 2
-
reserved
1 to 0
BUF[1:0]
Buffer:
00 — Buffers are not lled.
01 — One of the buffers is lled.
10 — One of the buffers is lled.
11 — Both the buffers are lled.
Table 45.
Endpoint MaxPacketSize register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
NTRANS[1:0]
FFOSZ[10:8]
Reset
-
00000
Bus reset
-
00000
Access
-
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FFOSZ[7:0]
Reset
00000000
Bus reset
00000000
Access
R/W
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