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參數(shù)資料
| 型號： | ISP1583ET1,118 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA64 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64 |
| 文件頁數(shù)： | 60/100頁 |
| 文件大?。?/td> | 508K |
| 代理商： | ISP1583ET1,118 |
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ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
61 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
9.5.2 Chip ID register (address: 70h)
This read-only register contains the chip identication and hardware version numbers.
The rmware must check this information to determine functions and features supported.
The register contains 3 bytes, and the bit allocation is shown in Table 84.
10
EP0RX
logic 1 indicates the endpoint 0 data RX buffer as interrupt source
9
-
reserved
8
EP0SETUP
logic 1 indicates that a SETUP token was received on endpoint 0
7
VBUS
logic 1 indicates a transition from LOW to HIGH on VBUS
6
DMA
DMA status: Logic 1 indicates a change in the DMA Interrupt Reason
register.
5
HS_STAT
High-Speed Status: Logic 1 indicates a change from full-speed to
high-speed mode (HS connection). This bit is not set, when the system
goes into full-speed suspend.
4
RESUME
Resume Status: Logic 1 indicates that a status change from suspend
to resume (active) was detected.
3
SUSP
Suspend Status: Logic 1 indicates that a status change from active to
suspend was detected on the bus.
2
PSOF
Pseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or
SOF
was received. Pseudo SOF is an internally generated clock signal
(full-speed: 1 ms period, high-speed: 125
s period) that is not
synchronized to the USB bus SOF or
SOF.
1
SOF
SOF Interrupt: Logic 1 indicates that a SOF or
SOF was received.
0
BRESET
Bus Reset: Logic 1 indicates that a USB bus reset was detected. When
bit OTG in the OTG register is set, BRESET will not be set, instead, this
interrupt bit will report SE0 on DP and DM for 2 ms.
Table 83.
Interrupt register: bit description …continued
Bit
Symbol
Description
Table 84.
Chip ID register: bit allocation
Bit
23
22
21
20
19
18
17
16
Symbol
CHIPID[15:8]
Reset
00010101
Bus reset
00010101
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
CHIPID[7:0]
Reset
10000010
Bus reset
10000010
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
VERSION[7:0]
Reset
00110000
Bus reset
00110000
Access
RRRRRRRR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1583ET1-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 SM FTPRINT RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET1TM | 制造商:STMicroelectronics 功能描述: |
| ISP1583ET2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB peripheral controller |
| ISP1583ET2,518 | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1583ET2-T | 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 DEVICE RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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