參數(shù)資料
型號(hào): ISP1583ET1,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, PLASTIC, SOT969-1,TFBGA-64
文件頁數(shù): 44/100頁
文件大?。?/td> 508K
代理商: ISP1583ET1,118
ISP1583_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
47 of 99
NXP Semiconductors
ISP1583
Hi-Speed USB peripheral controller
Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the
other control signals are not 3-stated.
9.4.1 DMA Command register (address: 30h)
The DMA Command register is a 1-byte register (for bit allocation, see Table 51) that
initiates all DMA transfer activity on the DMA controller. The register is write-only: reading
it will return FFh.
Remark: The DMA bus will be in 3-state, until a DMA command is executed.
DMA Hardware register
ENDIAN[1:0]
determines whether data is
to be byte swapped or
normal; applicable only in
16-bit mode
determines whether data is to
be byte swapped or normal;
applicable only in 16-bit mode
EOT_POL
selects polarity of the EOT
signal
input EOT is not used
MASTER
set to logic 0 (slave)
set to logic 1 (master)
ACK_POL,
DREQ_POL,
WRITE_POL,
READ_POL
selects polarity of DMA
handshake signals
selects polarity of DMA
handshake signals
Table 50.
Control bits for IDE-specied DMA transfers
Control bits
Description
Reference
MDMA read/write (opcode = 06h/07h)
DMA Conguration register
ATA_MODE
set to logic 1 (ATA transfer)
DMA_MODE[1:0]
selects MDMA mode; timing are ATA(PI) compatible
PIO_MODE[2:0]
selects PIO mode; timing are ATA(PI) compatible
DMA Hardware register
MASTER
set to logic 0
Table 49.
Control bits for Generic DMA transfers …continued
Control bits
Description
Reference
GDMA read/write
(opcode = 00h/01h)
MDMA (master) read/write
(opcode = 06h/07h)
Table 51.
DMA Command register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DMA_CMD[7:0]
Reset
11111111
Bus reset
11111111
Access
WWWWWWWW
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