參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 68/99頁
文件大?。?/td> 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
69 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
[1]
The reserved bits must always be written with the reset value.
11.3.4 FRINDEX register
The Frame Index (FRINDEX) register is used by the host controller to index into the
periodic frame list. The register updates every 125
s, once each microframe. Bits N to 3
are used to select a particular entry in the periodic frame list during periodic schedule
execution. The number of bits used for the index depends on the size of the frame list as
set by the system software in FLS[1:0] (bits 3 to 2) of the USBCMD register. This register
must be written as a DWORD. Byte writes produce undened results. This register cannot
be written unless the host controller is in the halted state, as indicated by HCH (bit 12 in
the USBSTS register). A write to this register while RS (bit 0 in the USBCMD register) is
set produces undened results. Writes to this register also affect the SOF value.
The bit allocation is given in Table 105.
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
IAAE
HSEE
FLRE
PCIE
USBERR
INTE
USBINTE
Reset
00000000
Access
R/W
Table 104. USBINTR - USB Interrupt Enable register bit description
Address: Content of the base address register + 28h
Bit
Symbol
Description
31 to 6
reserved
-
5
IAAE
Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS
register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software clearing bit IAA.
4
HSEE
Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the host
controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE.
3
FLRE
Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the host
controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR.
2
PCIE
Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the
host controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD.
1
USB
ERRINTE
USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set,
the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged
by software clearing bit USBERRINT.
0
USBINTE
USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the host
controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by
software clearing bit USBINT.
Table 105. FRINDEX - Frame Index register bit allocation
Address: Content of the base address register + 2Ch
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
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