參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 39/99頁
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
43 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
The register contains 4 bytes, and the bit allocation is given in Table 59.
[1]
The reserved bits must always be written with the reset value.
Table 59.
HcInterruptDisable - Host Controller Interrupt Disable register bit allocation
Address: Content of the base address register + 14h
Bit
31
30
29
28
27
26
25
24
Symbol
MIE
OC
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
RHSC
FNO
UE
RD
SF
WDH
SO
Reset
00000000
Access
R/W
Table 60.
HcInterruptDisable - Host Controller Interrupt Disable register bit description
Address: Content of the base address register + 14h
Bit
Symbol
Description
31
MIE
Master Interrupt Enable:
0 — Ignore
1 — Disables interrupt generation because of events specied in other bits of this register.
This eld is set after a hardware or software reset. Interrupts are disabled.
30
OC
Ownership Change:
0 — Ignore
1 — Disables interrupt generation because of ownership change.
29 to 7
reserved
-
6
RHSC
Root Hub Status Change:
0 — Ignore
1 — Disables interrupt generation because of root hub status change.
5
FNO
Frame Number Overow:
0 — Ignore
1 — Disables interrupt generation because of frame number overow.
4UE
Unrecoverable Error:
0 — Ignore
1 — Disables interrupt generation because of unrecoverable error.
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