參數(shù)資料
型號(hào)： ISP1564ET,551
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA100
封裝： 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù)： 35/99頁
文件大小： 493K
代理商： ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
39 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
[1]
The reserved bits must always be written with the reset value.
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
SOC[1:0]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
OCR
BLF
CLF
HCR
Reset
00000000
Access
R/W
Table 54.
HcCommandStatus - Host Controller Command Status register bit description
Address: Content of the base address register + 08h
Bit
Symbol
Description
31 to 18 reserved
-
17 to 16 SOC[1:0]
Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is initialized
to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is detected, even
if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor any persistent
scheduling problems.
15 to 4
reserved
-
3
OCR
Ownership Change Request: This bit is set by an OS HCD to request a change of control of the host
controller. When set, the host controller must set OC (bit 30 in HcInterruptStatus). After the
changeover, this bit is cleared and remains so until the next request from the OS HCD.
2
BLF
Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the
bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the host controller
begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the host
controller does not need to process the bulk list. If BLF is logic 1, the host controller must start
processing the bulk list and set BF to logic 0. If the host controller nds a TD on the list, then the host
controller must set BLF to logic 1, causing the bulk list processing to continue. If no TD is found on the
bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the host controller completes
processing the bulk list and the bulk list processing stops.
1
CLF
Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set
by the HCD whenever it adds a TD to an ED in the control list.
When the host controller begins to process the head of the control list, it checks CLF. If CLF is logic 0,
the host controller does not need to process the control list. If Control-Filled (CF) is logic 1, the host
controller needs to start processing the control list and set CLF to logic 0. If the host controller nds a
TD on the list, then the host controller must set CLF to logic 1, causing the control list processing to
continue. If no TD is found on the control list, and if the HCD does not set CLF, then CLF is still logic 0
when the host controller completes processing the control list and the control list processing stops.
0
HCR
Host Controller Reset: This bit is set by the HCD to initiate a software reset of the host controller.
Regardless of the functional state of the host controller, it moves to the USBSUSPEND state in which
most of the operational registers are reset, except those stated otherwise; for example, IR (bit 8) in the
HcControl register, and no host bus accesses are allowed. This bit is cleared by the host controller on
completing the reset operation. The reset operation must be completed within 10
s. This bit, when
set, must not cause a reset to the root hub and no subsequent reset signaling must be asserted to its
downstream ports.
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ISP1564ET-T 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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