參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 3/99頁
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
10 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
7.
Functional description
7.1 OHCI host controller
An OHCI host controller per port transfers data to devices at the Original USB dened bit
rate of 12 Mbit/s or 1.5 Mbit/s.
7.2 EHCI host controller
The EHCI host controller transfers data to a Hi-Speed USB compliant device at the
Hi-Speed USB dened bit rate of 480 Mbit/s. When the EHCI host controller has the
ownership of a port, OHCI host controllers are not allowed to modify the port register. All
additional port bit denitions required for the enhanced host controller are not visible to
the OHCI host controller.
7.3 Dynamic port-routing logic
The port-routing feature allows sharing of the same physical downstream ports between
the Original USB host controller and the Hi-Speed USB host controller. This requirement
of
Enhanced Host Controller Interface Specication for Universal Serial Bus Rev. 1.0
provides ports that are multiplexed with the ports of the OHCI.
The EHCI is responsible for the port-routing switching mechanism. Two register bits are
used for ownership switching. During power-on and system reset, the default ownership of
all downstream ports is the OHCI. The enhanced Host Controller Driver (HCD) controls
the ownership during normal functionality.
7.4 Hi-Speed USB analog transceivers
The Hi-Speed USB analog transceivers directly interface to the USB cables through
integrated termination resistors. These transceivers can transmit and receive serial data
at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s).
7.5 Power management
The ISP1564 provides an advanced power management capability interface that is
compliant with
PCI Bus Power Management Interface Specication Rev. 1.1. Power is
controlled and managed by the interaction between drivers and PCI registers.
For a detailed description on power management, see Section 10.
7.6 Phase-Locked Loop (PLL)
A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows
the use of a low-cost 12 MHz crystal, which also minimizes EMI.
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相關代理商/技術參數(shù)
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