參數(shù)資料
型號： ISP1564ET,551
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA100
封裝： 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù)： 17/99頁
文件大?。?/td> 493K
代理商： ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
23 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
8.2.2 Enhanced host controller-specic PCI registers
In addition to PCI conguration header registers, EHCI needs some additional PCI
conguration space registers to indicate the serial bus release number, downstream port
wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).
The EHCI-specic PCI registers are given in Table 25.
8.2.2.1
SBRN register
The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit
description is given in Table 26. This register contains the release number of the USB
specication with which this USB host controller module is compliant.
8.2.2.2
FLADJ register
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in Table 27.
[1]
The reserved bits must always be written with the reset value.
Table 25.
EHCI-specic PCI registers
Offset
Register
60h
Serial Bus Release Number (SBRN)
61h
Frame Length Adjustment (FLADJ)
62h to 63h
Port Wake Capability (PORTWAKECAP)
Table 26.
SBRN - Serial Bus Release Number register (address 60h) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
SBRN[7:0]
R
20h*
Serial Bus Specication Release Number: This register value is to identify
Universal Serial Bus Specication Rev. 2.0. All other combinations are reserved.
Table 27.
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved[1]
FLADJ[5:0]
Reset
00100000
Access
R/W
Table 28.
FLADJ - Frame Length Adjustment register (address 61h) bit description
Bit
Symbol
Description
7 to 6
reserved
-
5 to 0
FLADJ[5:0]
Frame Length Timing Value: Each decimal value change to this register corresponds to 16
high-speed bit times. The SOF cycle time, number of SOF counter clock periods to generate a
SOF microframe length, is equal to 59488 + value in this eld. The default value is decimal 32
(20h), which gives an SOF cycle time of 60000. See Table 29.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1564ETGA 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1564ET-S 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1564ET-T 功能描述:外圍驅(qū)動器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
ISP1564ETUM 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1564HL 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller
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