參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 29/99頁
文件大小: 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
34 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
11. USB host controller registers
Each host controller contains a set of on-chip operational registers that are mapped to
un-cached memory of the system addressable space. This memory space must begin on
a DWORD (32-bit) boundary. The size of the allocated space is dened by the initial value
in the Base Address register 0. HCDs must interact with these registers to implement USB
functionality.
After the PCI enumeration driver nishes the PCI device conguration, the new base
address of these memory-mapped operational registers is dened in BAR0. The HCD can
access these registers by using the address of base address value + offset.
Table 48 contains a list of host controller registers.
For the OHCI host controller, there are only operational registers for the USB operation.
For the enhanced host controller, there are two types of registers: one set of read-only
capability registers, and one set of read and write operational registers.
Table 48.
USB host controller registers
Address
OHCI register
Reset value
func0 OHCI[1]
EHCI register
Reset value
func2 EHCI[1]
00h
HcRevision
0000 0010h
CAPLENGTH/HCIVERSION[2]
0100 0020h
04h
HcControl
0000 0000h
HCSPARAMS
0000 1292h
08h
HcCommandStatus
0000 0000h
HCCPARAMS
0000 0012h
0Ch
HcInterruptStatus
0000 0000h
HCSP-PORTROUTE1[31:0]
0000 1010h
10h
HcInterruptEnable
0000 0000h
HCSP-PORTROUTE2[59:32]
0000 0000h
14h
HcInterruptDisable
0000 0000h
reserved
-
18h
HcHCCA
0000 0000h
reserved
-
1Ch
HcPeriodCurrentED
0000 0000h
reserved
-
20h
HcControlHeadED
0000 0000h
USBCMD
0008 0000h
24h
HcControlCurrentED
0000 0000h
USBSTS
0000 1000h
28h
HcBulkHeadED
0000 0000h
USBINTR
0000 0000h
2Ch
HcBulkCurrentED
0000 0000h
FRINDEX
0000 0000h
30h
HcDoneHead
0000 0000h
reserved
-
34h
HcFmInterval
0000 2EDFh
PERIODICLISTBASE
0000 0000h
38h
HcFmRemaining
0000 0000h
ASYNCLISTADDR
0000 0000h
3Ch
HcFmNumber
0000 0000h
reserved
-
40h
HcPeriodicStart
0000 0000h
reserved
-
44h
HcLSThreshold
0000 0628h
reserved
-
48h
HcRhDescriptorA
FF00 0902h
reserved
-
4Ch
HcRhDescriptorB
0006 0000h
reserved
-
50h
HcRhStatus
0000 0000h
reserved
-
54h
HcRhPortStatus[1]
0000 0000h
reserved
-
58h
HcRhPortStatus[2]
0000 0000h
reserved
-
5Ch
reserved
-
reserved
-
60h
reserved
-
CONFIGFLAG
0000 0000h
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