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參數(shù)資料
| 型號： | ISP1564ET,551 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA100 |
| 封裝： | 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100 |
| 文件頁數(shù)： | 10/99頁 |
| 文件大小： | 493K |
| 代理商： | ISP1564ET,551 |
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ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
17 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
8.2.1.4
Status register
The Status register is a 2-byte read-only register used to record status information on PCI
bus-related events. For bit allocation, see Table 8.
Table 8.
Status register (address 06h) bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
DPE
SSE
RMA
RTA
STA
DEVSELT[1:0]
MDPE
Reset
00000010
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
FBBC
reserved
66MC
CL
reserved
Reset
00010000
Access
RRRRRRRR
Table 9.
Status register (address 06h) bit description
Bit
Symbol
Description
15
DPE
Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if
the parity error handling is disabled.
14
SSE
Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that
never assert SERR# do not need to implement this bit.
13
RMA
Received Master Abort: This bit must be set by a master device whenever its transaction, except for
special cycle, is terminated with master abort. All master devices must implement this bit.
12
RTA
Received Target Abort: This bit must be set by a master device whenever its transaction is
terminated with target abort. All master devices must implement this bit.
11
STA
Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction
with target abort. Devices that never signal target abort do not need to implement this bit.
10 to 9
DEVSELT
[1:0]
DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to
assert DEVSEL#:
00b — Fast
01b — Medium
10b — Slow
11b — Reserved
These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any
bus command, except Conguration Read and Conguration Write.
8
MDPE
Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three
conditions are met:
The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write.
The agent setting the bit acted as the bus master for the operation in which error occurred.
PER (bit 6 in the Command register) is set.
7
FBBC
Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting
fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to
logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise.
6
reserved
-
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1564ETGA | 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1564ET-S | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1564ET-T | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI USB 2.0 2PORT PCI HOST CONTROL RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ISP1564ETUM | 功能描述:IC USB PCI HOST CTRLR 100-TFBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISP1564HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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