參數(shù)資料
型號(hào): ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁(yè)數(shù): 48/99頁(yè)
文件大?。?/td> 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
51 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
[1]
The reserved bits must always be written with the reset value.
11.1.16 HcFmNumber register
This register is a 16-bit counter, and the bit allocation is given in Table 79.
It provides a timing reference among events happening in the host controller and the HCD.
The HCD may use the 16-bit value specied in this register and generate a 32-bit frame
number, without requiring frequent access to the register.
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
FR[13:8]
Reset
00000000
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
FR[7:0]
Reset
00000000
Access
R/W
Table 78.
HcFmRemaining - Host Controller Frame Remaining register bit description
Address: Content of the base address register + 38h
Bit
Symbol
Description
31
FRT
Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) whenever
FR[13:0] reaches 0. This bit is used by the HCD for the synchronization between FI[13:0]
(bits 13 to 0 of HcFmInterval) and FR[13:0].
30 to 14
reserved
-
13 to 0
FR[13:0]
Frame Remaining: This counter is decremented at each bit time. When it reaches 0, it is reset by
loading the FI[13:0] value specied in HcFmInterval at the next bit time boundary. When entering
the USBOPERATIONAL state, the host controller reloads the content with FI[13:0] of
HcFmInterval and uses the updated value from the next SOF.
Table 79.
HcFmNumber - Host Controller Frame Number register bit allocation
Address: Content of the base address register + 3Ch
Bit
31
30
29
28
27
26
25
24
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
23
22
21
20
19
18
17
16
Symbol
reserved[1]
Reset
00000000
Access
R/W
Bit
15
14
13
12
11
10
9
8
Symbol
reserved[1]
FN[13:8]
Reset
00000000
Access
R/W
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