參數(shù)資料
型號: ISP1564ET,551
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA100
封裝: 9 X 9 MM, 0.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, SOT926-1, TFBGA-100
文件頁數(shù): 27/99頁
文件大?。?/td> 493K
代理商: ISP1564ET,551
ISP1564_2
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 02 — 13 November 2008
32 of 98
NXP Semiconductors
ISP1564
HS USB PCI host controller
The slave address that the ISP1564 uses to access the EEPROM is 101 0000b. Page
mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must
be connected to ground (logic 0).
9.3 Information loading from EEPROM
Figure 7 shows the content of the EEPROM memory. If the EEPROM is not present, the
default values of device ID, vendor ID, subsystem VID and subsystem DID assigned to
NXP Semiconductors by PCI-SIG will be loaded. For default values, see Table 3.
9.4 EEPROM programming
To simplify the manufacturing of products based on the ISP1564, which requires changing
of subsystem DID and VID, information can be written in-circuit to the EEPROM through
the PCI bus. Reading and writing of the EEPROM is achieved by the mechanism
described in Appendix I of
PCI Local Bus Specication Rev. 2.2.
Remark: The VPD data structure described in Appendix I of
PCI Local Bus Specication
Rev. 2.2 is not adopted and only the read write mechanism is adopted in the ISP1564.
10. Power management
10.1 PCI bus power states
The PCI bus can be characterized by one of the four power management states: B0, B1,
B2 and B3.
B0 state (PCI clock = 33 MHz, PCI bus power = on) — This corresponds to the bus
being fully operational.
L = LOW; H = HIGH.
Fig 7.
Information loading from EEPROM
004aaa930
subsystem vendor ID (L)
0
1
3
4
6
5
2
subsystem vendor ID (H)
subsystem device ID (L) - OHCI
subsystem device ID (H) - OHCI
subsystem device ID (L) - EHCI
subsystem device ID (H) - EHCI
reserved - FFh
signature
15h - loads subsystem vendor ID, device ID
1Ah - loads default values defined by NXP Semiconductors
7
address
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