參數(shù)資料
型號(hào): IS45VS16160D-8BLA2
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54
封裝: 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54
文件頁(yè)數(shù): 19/61頁(yè)
文件大小: 939K
代理商: IS45VS16160D-8BLA2
26
Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ
NOP
CAS Latency - 3
tAC
tOH
DOUT
T0
T1
T2
T3
T4
tLZ
CLK
COMMAND
DQ
READ
NOP
CAS Latency - 2
tAC
tOH
DOUT
T0
T1
T2
T3
tLZ
CAS LATENCY
CAS Latency
TheCASlatencyisthedelay,inclockcycles,between
the registrationofaREADcommandandtheavailabilityof
thefirstpieceofoutputdata.Thelatencycanbesettotwoor
three clocks.
IfaREADcommandisregisteredatclockedgen,and
the latency is m clocks, the data will be available by clock
edge n + m.TheDQswillstartdrivingasaresultofthe
clock edge one cycle earlier (n + m -1),andprovidedthat
the relevant access times are met, the data will be valid by
clock edge n + m.Forexample,assumingthattheclock
cycle time is such that all relevant access times are met,
ifaREADcommandisregisteredatT0andthelatency
isprogrammedtotwoclocks,theDQswillstartdriving
afterT1andthedatawillbevalidbyT2,asshowninCAS
Latency diagrams.The Allowable Operating Frequency
tableindicatestheoperatingfrequenciesatwhicheach
CAS latency setting can be used.
Reservedstatesshouldnotbeusedasunknownoperation
or incompatibility with future versions may result.
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
-75
100
133
-8
100
125
Operating Mode
ThenormaloperatingmodeisselectedbysettingM7andM8
tozero;theothercombinationsofvaluesforM7andM8are
reservedforfutureuseand/ortestmodes.Theprogrammed
burstlengthappliestobothREADandWRITEbursts.
Testmodesandreservedstatesshouldnotbeusedbe-
cause unknown operation or incompatibility with future
versions may result.
Write Burst Mode
WhenM9=0,theburstlengthprogrammedviaM0-M2
appliestobothREADandWRITEbursts;whenM9=1,
theprogrammedburstlengthappliestoREADbursts,but
writeaccessesaresingle-location(nonburst)accesses.
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