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參數(shù)資料
| 型號： | IS45VS16160D-8BLA2 |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 16 SYNCHRONOUS DRAM, 6 ns, PBGA54 |
| 封裝： | 13 X 8 MM, 0.80 MM PITCH, LEAD FREE, MS-207, BGA-54 |
| 文件頁數(shù)： | 13/61頁 |
| 文件大?。?/td> | 939K |
| 代理商： | IS45VS16160D-8BLA2 |
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Integrated Silicon Solution, Inc. — www.issi.com
Rev. 00A
04/21/09
IS42VS83200D, IS42VS16160D
IS45VS83200D, IS45VS16160D
FUNCTIONAL DESCRIPTION
The256MbSDRAMsarequad-bankDRAMswhichoperate
at1.8Vandincludeasynchronousinterface(allsignals
are registered on the positive edge of the clock signal,
CLK).Eachofthe67,108,864-bitbanksisorganizedas
8,192rowsby512columnsby16bitsor8,192rowsby
1,024columnsby8bits.
ReadandwriteaccessestotheSDRAMareburstoriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVEcommandwhichisthenfollowedbyaREADor
WRITEcommand.Theaddressbitsregisteredcoincident
withtheACTIVEcommandareusedtoselectthebank
and row to be accessed (BA0andBA1selectthebank,A0-
A12selecttherow).TheaddressbitsA0-A9(x8);A0-A8(x16)
registeredcoincidentwiththeREADorWRITEcommand
are used to select the starting column location for the
burst access.
Prior to normal operation, the SDRAM must be initial-
ized.Thefollowingsectionsprovidedetailedinformation
coveringdeviceinitialization,registerdefinition,command
descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner.
The256MbSDRAMisinitializedafterthepowerisapplied
toVddandVddq(simultaneously)andtheclockisstable
withDQMHighandCKEHigh.
A200sdelayisrequiredpriortoissuinganycommand
other than a COMMANDINHIBIT or a NOP.TheCOMMAND
INHIBITorNOPmaybeappliedduringthe200usperiodand
should continue at least through the end of the period.
WithatleastoneCOMMANDINHIBITorNOPcommand
havingbeenapplied,aPRECHARGEcommandshould
be applied once the 200s delay has been satisfied. All
banksmustbeprecharged.Thiswillleaveallbanksinan
idle state after which at least eight AUTOREFRESH cycles
must be performed. After the AUTOREFRESH cycles are
complete, the SDRAM is then ready for mode register
programming.
The mode register should be loaded prior to applying
any operational command because it will power up in an
unknown state.
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