參數(shù)資料
型號(hào)： IBM13Q8739CC
廠商： IBM Microeletronics
英文描述： 8M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（8M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 8米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（8米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁數(shù)： 7/56頁
文件大?。?/td> 903K
代理商： IBM13Q8739CC
IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 56
Burst Mode Operation
Burst Mode operation is used to provide a constant flow of data to memory locations (Write cycle) or from
memory locations (Read cycle). Three parameters define Burst Mode operation: Burst sequence, burst
length, and operation mode. The burst sequence and burst length are programmable and are determined by
address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is
set by address bits A7 - A10 and BS.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM.
Two types of burst sequences are supported: sequential and interleaved, as the table below shows.
The burst length controls the number of bits that will be output after a Read command, or the number of bits
to be input after a Write command. The burst length can be programmed to have values of 1, 2, 4, 8, or full
page. (The actual page length is dependent on organization: x4, x8, or x16.) Full-page Burst operation is only
possible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single Write operation. Normal operation
implies that the device will perform Burst operations on both Read and Write cycles until the desired burst
length is satisfied. Multiple burst with single Write operation was added to support Write Through Cache oper-
ation, where the programmed burst length applies only to Read cycles. All Write cycles are single Write oper-
ations when this mode is selected.
Bank Activate Command
The Bank Activate command is issued by holding CAS and WE high with S0/S1 on one deck and RAS low at
the rising edge of the clock. The bank select address, A11/BS is used to select the desired bank. If BS is low,
bank A is activated; if BS is high, bank B is activated. Row address A0 - A10 selects the active row in the
selected bank.
Burst Length and Sequence
(This DIMM supports burst lengths of 2 only.)
Burst Length
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
2
x x 0
0, 1
0, 1
x x 1
1, 0
1, 0
4
x 0 0
0, 1, 2, 3
0, 1, 2, 3
x 0 1
1, 2, 3, 0
1, 0, 3, 2
x 1 0
2, 3, 0, 1
2, 3, 0, 1
x 1 1
3, 0, 1, 2
3, 2, 1, 0
8
0 0 0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
0 0 1
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
0 1 0
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
0 1 1
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
1 0 0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1 0 1
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
1 1 0
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
1 1 1
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
Full Page (see
note)
n n n
Cn, Cn+1, Cn+2,......
Not Supported
Note: Page length is a function of I/O organization and column addressing; the x4 SDRAMs used on this DIMM have a Page Length
equal to 1024 bits.
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