參數(shù)資料
型號(hào)： IBM13Q8739CC
廠商： IBM Microeletronics
英文描述： 8M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（8M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 8米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（8米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁(yè)數(shù)： 3/56頁(yè)
文件大?。?/td> 903K
代理商： IBM13Q8739CC
IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 56
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0
Input
Pulse
Positive
Edge
The system clock input. All the SDRAM inputs are sampled on the rising edge of the
clock.
Activates the CK0 signal when high and deactivates the CK0 signal when low. By deacti-
vating the clock, CKE0 low initiates the Power Down mode, the Suspend mode, or the
Self Refresh mode.
Chip selects enable the command decoders, when low, in the assorted chips and disable
the command decoder when high. When the command decoder is disabled, new com-
mands are ignored but previous operations continue. Each of the chip selects controls
one of the physical DIMM banks. S0 enables the lower deck of each stacked SDRAM
and S1 enables the upper deck.
Active Lowoperation to be executed by the SDRAM.
During a Bank Activate command cycle, A0-A10/AP defines the row address (RA0-
RA10) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, A10/AP is
used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If
A10/AP is high, autoprecharge is selected and A11/BS defines the bank to be pre-
charged (low=bank A, high=bank B). If A10/AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with A11/BS to con-
trol which bank(s) to precharge. If A10/AP is high, both bank A and bank B will be pre-
charged regardless of the state of A11/BS. If A10/AP is low, then A11/BS is used to
define which bank to precharge.
CKE0
Input
Level
Active
High
S0, S1
Input
Pulse
Active Low
RAS, CAS
WE
Input
Pulse
A0 - A9,
A10/AP
A11/BS
Input
Level
—
DQ0 - DQ71
Input
Output
Level
—
Data Input/Output pins operate in the same manner as on conventional DRAM DIMMs.
DQM
Input
Pulse
Mask
Active
High
The Data Input/Output mask places the DQ buffers in a high-impedance state when sam-
pled high. In Read mode, DQM has a latency of three clock cycles and controls the out-
put buffers like an output enable. In Write mode, DQM has a latency of one and operates
as a word mask by allowing input data to be written if it is low but blocking the Write oper-
ation if it is high.
VDD, VSS
Supply
Power and ground for the input buffers and the core logic.
Presence Detect
Pin
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
ID1
ID2
ID3
Value
0
1
0
0
1
0
1
1
1
0
0
Notes
1
1
1
1
1
1
1
1
2
2
2
1. 0 = driven to V
OL
, 1 = open
2. 0 = ground, 1 = open
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