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參數(shù)資料
| 型號： | IBM13Q8739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結(jié)構(gòu)）) |
| 中文描述： | 8米× 72注冊內(nèi)存模塊（帶寄存同步動態(tài)內(nèi)存模塊（8米× 72高速存儲器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 16/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | IBM13Q8739CC |
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IBM13Q8739CC
8M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 56
08J0513.E24526
Revised 4/98
Precharge Command
The Precharge command is used to precharge or close a bank that has been activated. The Precharge com-
mand is triggered when S0/S1 on one deck, RAS and WE are low and CAS is high at the rising edge of the
clock. The Precharge command can be used to precharge each bank separately or both banks simulta-
neously. Two address bits--A10/AP and A11 (BS)--define the bank(s) to be precharged when the command is
issued.
For Read cycles, the Precharge command may be applied coincident with the second to last clock of the
Burst Read cycle.
For Write cycles, however, a delay must be satisfied from the start of the last Burst Write cycle until the Pre-
charge command can be issued. This delay is known as t
DPL
, Data-in to Precharge delay.
After the Precharge command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge command and the Activate command must be
greater than or equal to the Precharge time (t
RP
).
Automatic Refresh Command (CAS before RAS Refresh)
When S0/S1 on one deck, RAS and CAS are held low with CKE0 and WE high at the rising edge of the clock,
the chip enters the Automatic Refresh mode (CBR). Both SDRAM banks of each deck must be precharged
and idle for a minimum of the Precharge time (t
RP
) before the Auto Refresh command (CBR) can be applied.
An address counter, internal to the device, decrements the word and bank address during the Refresh cycle.
Burst Write with Auto-Precharge
(Burst Length = 2, CAS latency = 2)
Bank Selection for Precharge by Address Bits
A10/AP
A11/BS
Precharged Bank(s)
LOW
LOW
Bank A only
LOW
HIGH
Bank B only
HIGH
DON’T CARE
Both Banks A and B
COMMAND
NOP
NOP
NOP
NOP
Auto-Precharge
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
NOP
BANK A
ACTIVE
NOP
NOP
DIN A0
DIN A1
t
DAL
*
t
CK2,
DQs
CAS latency = 2
Begin Autoprecharge
Bank can be reactivated at completion of tDAL
*
Note: Data is delayed one cycle due to on-DIMM pipeline register
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