參數(shù)資料
型號(hào)： IBM13T16644NPA
廠商： IBM Microeletronics
英文描述： 16M x 64 PC100 SDRAM(1MB PC100 同步動(dòng)態(tài)RAM)
中文描述： 16米x 64 PC100的SDRAM內(nèi)存（1MB的PC100的同步動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 1/17頁(yè)
文件大?。?/td> 407K
代理商： IBM13T16644NPA
IBM13T16644NPA
16M x 64 PC100 SDRAM SO DIMM
09K1470.E92279
11/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 17
Features
144 Pin JEDEC Standard, 8 Byte Small Outline
Dual-In-line Memory Module
16Mx64 Synchronous DRAM SO DIMM
Performance PC100
Inputs and outputs are LVTTL (3.3V) compatible
10 Ohm Resistors on DQ’s
Single 3.3V
±
0.3V Power Supply
Single Pulsed RAS interface
SDRAMs have 4 internal banks
Fully Synchronous to positive Clock Edge
Data Mask for Byte Read/Write control
Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (Full-
Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Suspend Mode and Power Down Mode
12/9/2 Addressing (Row/Column/Bank)
4096 refresh cycles distributed across 64ms
Serial Presence Detect
Card size: 2.66" x 1.25" x 0.149"
Gold contacts
SDRAM
S
in TSOP Type II Package
Description
IBM13T16644NPA is a 144-pin Synchronous DRAM
Small Outline Dual In-line Memory Module (SO
DIMM) which is organized as a 16Mx64 high-speed
memory array. The SO DIMM uses eight 8Mx16
SDRAMs in 400mil TSOP II packages. The SO -
DIMM achieves high speed data transfer rates of up
to 100MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
The SO DIMM is intended to comply with all JEDEC
and INTEL PC100 rev 1.0 standards set for 144 pin
SDRAM SO DIMMs.
All control, address, and data input/output circuits
are synchronized with the positive edge of the exter-
nally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK1). Internal oper-
ating modes are defined by combinations of the
Card Outline
RAS, CAS, WE, S0, S1, DQMB, and CKE0, CKE1,
signals. A command decoder initiates the necessary
timings for each operation. A 12 bit address bus
accepts address information in a row/column multi-
plexing arrangement.
Prior to any access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the SO DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The SO DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 144-pin SO DIMMs provide a high perfor-
mance, flexible 8-byte interface in a 2.66" long
space-saving footprint.
-360
3
Units
CAS Latency
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
100
MHz
10
ns
6
ns
1
2
143
144
(
Front)
(Back)
59
60
61
62
.
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