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| 型號(hào)： | IBM13T16644NPA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 64 PC100 SDRAM(1MB PC100 同步動(dòng)態(tài)RAM) |
| 中文描述： | 16米x 64 PC100的SDRAM內(nèi)存（1MB的PC100的同步動(dòng)態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大?。?/td> | 407K |
| 代理商： | IBM13T16644NPA |
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IBM13T16644NPA
16M x 64 PC100 SDRAM SO DIMM
09K1470.E92279
11/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 17
Operating, Standby and Refresh Currents
(T
A
= 0 to +70C, V
CC
= 3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Speed/Organization
Units
Notes
-360/16Mx64
Operating Current
t
RC
=
t
RC
(min), t
CK
= min
Active-Precharge command cycling
without Burst operation
I
CC1
1 bank operation
480
mA
1, 3, 4
Precharge Standby Current in
Power Down Mode
I
CC2P
CKE
≤
V
IL
(max), t
CK
= min, S0, S1
=V
IH
(min)
8
mA
2
I
CC2Ps
CKE
≤
V
IL
(max), t
CK
= Infinity, S0, S1
=V
IH
(min)
8
mA
2
Precharge Standby Current in Non-
Power Down Mode
I
CC2N
CKE
≥
V
IH
(min), t
CK
= min, S0, S1 =V
IH
(
min)
280
mA
2, 5
I
CC2NS
CKE
≥
V
IH
(min), t
CK
= Infinity, S0, S1
=V
IH
(min)
80
mA
2
No Operating Current
(Active state: 4 bank)
I
CC3N
CKE
≥
V
IH
(min), t
CK
= min, S0, S1 =V
IH
(
min)
320
mA
2, 5
I
CC3P
CKE
≤
V
IL
(max), t
CK
= min, S0, S1 =V
IH
(
min) (Power Down Mode)
80
mA
2
Burst Operating Current
I
CC4
t
CK
= min, Read/ Write command
cycling
520
mA
1, 4, 5
Auto (CBR) Refresh Current
I
CC5
t
CK
= min, CBR command cycling
900
mA
1, 6
Self Refresh Current
I
CC6
CKE0
≤
0.2V
6.4
mA
6
Serial PD Device Standby Current
I
SB5
V
IN
= GND or V
CC
30
μ
A
7
Serial PD Device Active Power Sup-
ply Current
I
CCA
SCL Clock Frequency = 100KHz
1
mA
8
1. The specified values are for one SO DIMM bank in the specified mode and the other SO DIMM bank in Active Standby (I
CC3N
).
2. The specified values are for both SO DIMM banks operating in the specified mode.
3. Input signals are changed up to three times during t
RC
(min). This assumes the 14 Row Address mode with four-bank operation
using rows A0-A11 and BA0-BA1.
4. The specified values are obtained with the outputs open.
5. Input signals are changed once during three clock cycles.
6. 64ms refresh time (15.6
μ
s, 4K refresh).
7. V
CC
= 3.3V.
8. Input pulse levels V
CC
x 0.1 to V
CC
x 0.9, Input rise and fall times 10ns, Input and output timing levels V
CC
x 0.5, Output load 1 TTL
gate and CL=100pf
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