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參數(shù)資料
| 型號： | IBM13T16644NPA |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 64 PC100 SDRAM(1MB PC100 同步動態(tài)RAM) |
| 中文描述： | 16米x 64 PC100的SDRAM內(nèi)存（1MB的PC100的同步動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 5/17頁 |
| 文件大小： | 407K |
| 代理商： | IBM13T16644NPA |
IBM13T16644NPA
16M x 64 PC100 SDRAM SO DIMM
09K1470.E92279
11/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 17
Serial Presence Detect
(Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry
(Hexadecimal)
80
08
04
0C
09
02
4000
01
A0
60
00
80
10
00
Notes
0
1
2
3
4
5
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Banks
Data Width of Assembly
Voltage Interface Level of this Assembly
SDRAM Device Cycle Time at CL=3
SDRAM Device Access Time from Clock at CL=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Device Width
Error Checking SDRAM Device Width
SDRAM Device Attr: Min Clk Delay, Random Col
Access
SDRAM Device Attributes: Burst Lengths Supported
SDRAM Device Attributes: Number of Device Banks
SDRAM Device Attributes: CAS Latencies Supported
SDRAM Device Attributes: CS Latency
SDRAM Device Attributes: WE Latency
SDRAM Module Attributes
128
256
SDRAM
12
9
2
x64
LVTTL
10.0ns
6.0ns
Non-Parity
SR/1x(15.625us)
x16
N/A
6 - 7
8
9
10
11
12
13
14
15
1 Clock
01
16
17
18
19
20
21
1,2,4,8, Full Page
4
2, 3
0
0
Unbuffered
Wr-1/Rd Burst, Pre-
charge All, Auto-Pre-
charge, V
CC
+/- 10%
15.0ns
9.0ns
N/A
N/A
8F
04
06
01
01
00
22
SDRAM Device Attributes: General
0E
23
24
25
26
Minimum Clock Cycle at CL=2
Maximum Data Access Time (t
AC
) from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time (t
AC
) from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
36 - 61 Reserved
62
SPD Revision
63
Checksum for bytes 0 - 62
F0
90
00
00
27
20ns
14
28
20ns
14
29
20ns
14
30
31
32
33
34
35
50ns
64MB
2.0ns
1.0ns
2.0ns
1.0ns
Undefined
1.2A
Checksum Data
32
10
20
10
20
10
00
12
cc
1
1. cc = Checksum Data byte, 00-FF (Hex)
2. “R” = Alphanumeric revision code, A-Z, 0-9
3. rr = ASCII coded revision code byte “R”
4. yy = Binary coded decimal year code, 00-99 (Decimal)
‘
00-63 (Hex)
5. ww = Binary coded decimal week code, 01-52 (Decimal)
‘
01-34 (Hex)
6. ss = Serial number data byte, 00-FF (Hex)
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