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| 型號： | IBM13Q8739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結構）) |
| 中文描述： | 8米× 72注冊內存模塊（帶寄存同步動態(tài)內存模塊（8米× 72高速存儲器陣列結構）） |
| 文件頁數(shù)： | 14/56頁 |
| 文件大小： | 903K |
| 代理商： | IBM13Q8739CC |
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IBM13Q8739CC
8M x 72 Registered SDRAM Module
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 56
08J0513.E24526
Revised 4/98
Burst Stop Command
Once a Burst Read or Write operation has been initiated, several methods allow terminating the Burst opera-
tion prematurely. These methods include using another Read or Write command to interrupt an existing Burst
operation, using a Precharge command to interrupt a Burst cycle and close the active bank, or using the
Burst Stop command to terminate the existing Burst operation but leave the bank open for future Read or
Write commands to the same page of the active bank.
Interrupting a burst with another Read or Write command requires care to avoid DQ contention. The Burst
Stop command, however, has the fewest restrictions, making it the easiest method to use when terminating a
Burst operation before it has been completed. The Burst Stop command is defined by having RAS and CAS
high with S0/S1 on one deck and WE low at the rising edge of the clock.
When using the Burst Stop command during a Burst Read cycle, the data DQs go to a high impedance state
after a delay which is equal to the CAS Latency set in the Mode Register plus one cycle.
If a Burst Stop command is issued during a Burst Write operation, any residual data from the Burst Write
cycle will be ignored. Data that is presented on the DQ pins up to and including the cycle when the Burst Stop
command is registered will be written to the memory.
Termination of a Burst Read Operation
(Burst Length = 2, CAS latency = 2)
Termination of a Burst Write Operation
(Burst Length = 2, CAS latency = 2)
COMMAND
READ A
Burst
Stop
NOP
NOP
NOP
NOP
t
CK2,
DQs
CAS latency = 2
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
DOUT A0
Note: Data is delayed one cycle due to on-DIMM pipeline register
COMMAND
NOP
WRITE A
Burst
Stop
NOP
NOP
NOP
NOP
DIN A0
CK0
T0
T2
T1
T3
T4
T5
T6
T7
T8
Input data for the Write is masked.
DQs
CAS latency = 2,3
don’t care
Note: Data is delayed one cycle due to on-DIMM pipeline register
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