參數(shù)資料
型號： IBM13Q8739CC
廠商： IBM Microeletronics
英文描述： 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結構）)
中文描述： 8米× 72注冊內存模塊（帶寄存同步動態(tài)內存模塊（8米× 72高速存儲器陣列結構））
文件頁數(shù)： 29/56頁
文件大小： 903K
代理商： IBM13Q8739CC
IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 29 of 56
Common Parameters
Symbol
Parameter
Value
Units
t
S0
Command Setup Time
2.3
—
ns
t
CH
Command Hold Time
1.3
—
ns
t
AS
Address and Bank Select Set-up Time
2.3
—
ns
t
AH
Address and Bank Select Hold Time
1.3
—
ns
t
RCD
RAS to CAS Delay
30
—
ns
t
RC
Bank Cycle Time
90
120000
ns
t
RAS
Active Command Period
60
120000
ns
t
RP
Precharge Time
30
—
ns
t
RRD
Bank to Bank Delay Time
20
—
ns
t
CCD
CAS to CAS Delay Time (Same Bank)
1
—
CK0
Refresh Cycle
Symbol
Parameter
Value
Units
Notes
Min.
Max.
t
REF
Refresh Period
—
64
ms
1, 2
t
SREX
Self Refresh Exit Time
3CK0 + ONE
t
RC
—
ns
3
1. 4096 cycles.
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake
up” the device.
3. Self Refresh Exit is an asynchronous operation. Self Refresh Exit is accomplished by starting the clock (CK0) then asserting CKE0
high. During the exit time (t
SREX
), no commands may be issued until t
RC
is satisfied and CKE0 must remain high. It is recom-
mended to hold S0, S1 high during the self refresh exit time, but NOP commands may be issued with each rising clock edge during
this period as an alternative.
Read Cycle
Symbol
Parameter
Value
Units
Notes
t
OH
Data Out Hold Time
3.3
—
ns
t
LZ
Data Out to Low Impedance Time
3.3
—
ns
t
HZ2
Data Out to High Impedance Time
3.3
10.8
ns
1
t
DQZ
DQM Data Out Disable Latency
3
—
CK0
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
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