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| 型號： | IBM13Q8739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(帶寄存同步動態(tài)RAM模塊（8M x 72高速存儲器陣列結構）) |
| 中文描述： | 8米× 72注冊內存模塊（帶寄存同步動態(tài)內存模塊（8米× 72高速存儲器陣列結構）） |
| 文件頁數： | 19/56頁 |
| 文件大小： | 903K |
| 代理商： | IBM13Q8739CC |
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IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 19 of 56
Command Truth Table
All the SDRAM operations are defined by states of S0/S1, WE, RAS, CAS, and DQM at the positive
rising edge of the clock. Only one deck can be operated at once, except during self refresh.
Function
CKE0
S0, S1
RAS
CAS
WE
DQM
A11/BS
A10/AP
A9 - A0
Notes
Previous
Cycle
Current
Cycle
Mode Register Set
H
X
L
L
L
L
X
OP Code
Auto (CBR) Refresh
H
H
L
L
L
H
X
X
X
X
Entry Self Refresh
H
L
L
L
L
H
X
X
X
X
Single Bank Precharge
H
X
L
L
H
L
X
BS
L
X
1
Precharge all Banks
H
X
L
L
H
L
X
X
H
X
Bank Activate
H
X
L
L
H
H
X
BS
Row Address
1
Write
H
X
L
H
L
L
X
BS
L
Column
1
Write with Auto-Precharge
H
X
L
H
L
L
X
BS
H
Column
1
Read
H
X
L
H
L
H
X
BS
L
Column
1
Read with Auto-Precharge
H
X
L
H
L
H
X
BS
H
Column
1
Burst Termination
H
X
L
H
H
L
X
X
X
X
2
No Operation
H
X
L
H
H
H
X
X
X
X
Device Deselect
H
X
H
X
X
X
X
X
X
X
Clock Suspend/Standby Mode
L
X
X
X
X
X
X
X
X
X
3
Data Write/Output Enable
H
X
X
X
X
X
L
X
X
X
4
Data Mask/Output Disable
H
X
X
X
X
X
H
X
X
X
4
Power Down Mode Entry
X
L
H
X
X
X
X
X
X
X
5
Power Down Mode Exit
X
H
H
X
X
X
X
X
X
X
5
1. Bank Select (BS), if BS = 0 then bank A is selected, if BS = 1 then bank B is selected.
2. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
3. During normal access mode, CKE0 is held high and CK0 is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
4. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock tim-
ing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
5. All banks must be precharged before entering the Power Down mode. The Power Down mode does not perform any Refresh oper-
ations; therefore the device can’t remain in this mode longer than the Refresh period (t
REF
) of the device. One clock delay is
required for mode entry and exit.
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