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參數(shù)資料
| 型號(hào)： | IBM13Q8739CC |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（8M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）) |
| 中文描述： | 8米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（8米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)）） |
| 文件頁數(shù)： | 5/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | IBM13Q8739CC |
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IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 56
Functional Operational Descriptions
Power On and Initialization
The default power-on state of the mode register is supplier specific and may be undefined. The following
power-on and initialization sequence guarantees the device is preconditioned to each user’s specific needs.
Like conventional DRAMs, the Synchronous DRAMs on the DIMM must be powered up and initialized in a
predefined manner. During power on, all VDD pins must be built up simultaneously to the specified voltage no
later than any of the input signal voltages. The power-on voltage must not exceed VDD+0.3V on any of the
input pins or VDD supplies. After power on, an initial pause of 100
μ
s is required, followed by a precharge of
both banks using the Precharge command. In an attempt to reduce the possibility of data contention on the
DQ bus during power on, it is recommended that the DQM pin be held high during the initial pause period.
Once both banks have been precharged, a minimum of two Auto Refresh cycles (CBR) must occur before the
Mode Register can be programmed. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
(Refer to page 8.) For application flexibility, CAS latency, burst length, burst sequence, and operation type
are user-defined variables and must be programmed into the SDRAM Mode Register with a single Mode
Register Set command. Any content of the Mode Register can be altered by re-executing the Mode Register
Set command. If the user chooses to modify only a subset of the Mode Register variables, all four variables
must be redefined when the Mode Register Set command is issued.
After initial power up, the Mode Register Set command must be issued before Read or Write cycles may
begin. Both banks on each deck must be in a precharged state and CKE0 must be high at least one cycle
before the Mode Register Set command can be issued. The Mode Register Set command is activated by the
low signals of RAS, CAS, S0/S1, and WE at the positive edge of the clock. The address input data during this
cycle defines the parameters to be set as shown in the Mode Register Operation table. After the mode regis-
ter set command is issued, two clocks are required before a new command may be issued.
CAS Latency
CAS latency defines the delay from when a Read command is registered on a rising clock edge to when the
data from that Read command becomes available at the outputs. The CAS latency is expressed in terms of
clock cycles, and for this specific DIMM a value of three cycles is supported. Do not confuse DIMM CAS
latency with the SDRAM CAS latency, which is one clock less. Once the appropriate CAS latency has been
selected it must be programmed into the mode register after power up. For an explanation of this procedure
see the previous section, Programming the Mode Register.
Registered DIMM Operation
All control and address signals are registered on-DIMM and thus are delayed by one cycle in arriving at the
SDRAMs. This pipelining allows the path between the memory controller and the DIMMs to be achieved in
two clock cycles rather than one. Use of an on-board register also reduces capacitive loading on DIMM input
signals. All timing diagrams show DIMM operation at the tabs, not SDRAM operation. Also, the on-DIMM PLL
must be given enough clock cycles to stabilize (Tstab) before any operation can be guaranteed.
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