參數(shù)資料
型號(hào)： IBM13Q8739CC
廠商： IBM Microeletronics
英文描述： 8M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（8M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 8米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（8米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁(yè)數(shù)： 1/56頁(yè)
文件大?。?/td> 903K
代理商： IBM13Q8739CC
IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 56
IBM0316409C 4M x 412/10, 3.3V, SR. IBM0316169C 1M x 1612/8, 3.3V, SR. IBM0316809C 2M x 812/9, 3.3V, SR.
Features
200-Pin JEDEC Standard, Buffered 8-Byte Dual
In-Line Memory Module
8M x 72 Synchronous DRAM DIMM
Performance:
CAS Latency = 2*
f
CK
Clock Frequency
t
CK2
Clock Cycle
t
AC2
Clock Access Time
* SDRAM CAS latency = 2; DIMM CAS Latency = 3
All inputs and outputs are LVTTL (3.3V) compat-
ible
Single 3.3V to 3.6V Power Supply
Single Pulsed RAS interface
Fully Synchronous to positive Clock Edge
Programmable Operation:
- SDRAM CAS Latency: 2
- Burst Type: Sequential or Interleave
- Burst Length: 2
- Operation: Burst Read and Write, or Multi-
ple Burst Read with Single Write
Data Mask control
Auto Refresh (CBR) and Self Refresh
Automatic and controlled Precharge Commands
Suspend Mode and Power Down Mode
11/10/1 Addressing (Row/Column/Bank); 2 decks
4096 refresh cycles distributed across 64ms
Parallel Presence Detect
Card size: 6.05" x 1.5" x 0.320"
Gold contacts
SDRAM
S
in TSOJ Type II, 2-High, Stacked
package
Description
IBM13Q8739CC is a buffered 200-pin Synchronous
DRAM Dual In-Line Memory Module (DIMM) which
is organized as an 8Mx72 high-speed memory
array. The DIMM uses eighteen 8Mbit x 4 SDRAMs
in 400mil TSOJ Type II Stacked packages. Each
stacked package contains two decks, individually
selectable for a total of 36 devices. The DIMM
achieves high-speed data-transfer rates of up to
66MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
The DIMM is intended to comply with all non-
optional JEDEC standards set for the 200-pin buff-
ered SDRAM DIMMs.
All control and address signals are synchronized
with the positive edge of an externally supplied
clock. They are latched in an on-DIMM pipeline reg-
ister and are presented to the SDRAMs on the fol-
lowing clock.
Prior to any Access operation, the CAS latency,
burst type, burst length, and burst operation type
must be programmed into the DIMM by address
inputs A0-A11 using the mode register set cycle.
The DIMM uses parallel presence detects imple-
mented according to the JEDEC standard.
All IBM 200-pin DIMMs provide a high performance,
flexible 8-byte interface in a 6.05” long high-perfor-
mance footprint. Related products include both EDO
DRAM and SDRAM unbuffered DIMMs in both non-
parity x64 and ECC-Optimized x72 configurations in
the 168-pin form factor.
Auto Refresh (CBR) and Self Refresh operation is
supported. Refreshing both decks simultaneously is
allowable during Self Refresh. All other operations
must be performed on a single deck at a time.
-10
66
15
11.3
Units
MHz
ns
ns
Card Outline
1
101
16
116
17
117
(Front)
(Back)
78
178
79
179
100
200
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