參數(shù)資料
型號(hào)： IBM13Q8739CC
廠商： IBM Microeletronics
英文描述： 8M x 72 Registered SDRAM Module(帶寄存同步動(dòng)態(tài)RAM模塊（8M x 72高速存儲(chǔ)器陣列結(jié)構(gòu)）)
中文描述： 8米× 72注冊(cè)內(nèi)存模塊（帶寄存同步動(dòng)態(tài)內(nèi)存模塊（8米× 72高速存儲(chǔ)器陣列結(jié)構(gòu)））
文件頁數(shù)： 17/56頁
文件大?。?/td> 903K
代理商： IBM13Q8739CC
IBM13Q8739CC
8M x 72 Registered SDRAM Module
08J0513.E24526
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 56
No control of the external address pins is required once this cycle has started. The Auto Refresh cycle
restores the word line after the sense amplifiers are set, eliminating the need to apply externally a Precharge
command.
When the Refresh cycle has completed, both SDRAM banks will be in the precharged (idle) state. A delay
between the Auto Refresh command (CBR) and the next Activate command or subsequent Auto Refresh
command must be greater than or equal to the RAS cycle time (t
RC
).
Note that this DIMM supports CBR on only one deck at a time.
Self Refresh Command
The SDRAMs on the DIMM have built-in timers to accommodate Self Refresh operation. The Self Refresh
command is defined by having S0/S1 on one deck, RAS, CAS and CKE0 held low with WE high at the rising
edge of the clock. Once the command is registered, CKE0 must be held low to keep the device in Self
Refresh mode. When the SDRAMs enter Self Refresh mode, all the external control signals, except CKE0,
are masked after a clock cycle delay. The clock is internally disabled during Self Refresh operation to save
power. The user may halt the external clock while the device is in Self Refresh mode; however, the clock
must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the SDRAMs
will exit Self Refresh operation on the third positive clock transition after CKE0 is returned high. A minimum
delay time is required when the device exits Self Refresh operation and before the next command can be
issued. This delay is equal to the RAS cycle time t
RC
, which is five clocks for this DIMM.
Data Mask
The SDRAM DIMM has a Data Mask function that can be used in conjunction with data Read and Write
cycles. When the Data Mask is activated (DQM high) during a Write cycle, the Write operation is prohibited
on the next cycle. If the Data Mask is activated during a Read cycle, the data outputs are disabled and
become high impedance after a three-clock delay, independent of CAS latency.
No Operation Command
The No Operation command should be used in cases when the SDRAMs are in a idle or a wait state. The
purpose of the No operation command is to prevent the SDRAMs from registering any unwanted commands
between operations. A No operation command is registered when S0/S1 on one deck is low with RAS, CAS,
and WE held high at the rising edge of the clock. A No operation command will not terminate a previous oper-
ation that is still executing, such as a Burst Read or Write cycle.
Deselect Command
The Deselect command performs the same function as a No operation command. Deselect command occurs
when S0/S1 is brought high; the RAS, CAS, and WE signals become don’t cares.
Power Down Mode
In order to reduce standby power consumption, a Power Down mode is available. All banks must be pre-
charged and the necessary Precharge delay (t
RP
) must occur before the SDRAMs can enter the Power Down
mode. Once the Power Down mode is initiated by holding CKE0 low, all receiver circuits except CK0 and
CKE0 are gated off. The Power Down mode does not perform any Refresh operations; therefore the device
can’t remain in Power Down mode longer than the Refresh period (t
REF
) of the device.
The Power Down mode is exited by bringing CKE0 high. A two-clock delay after the registration of CKE0 high
is required for the SDRAMs to exit the Power Down mode.
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