參數(shù)資料
型號(hào): HB52E169EN
廠商: Hitachi,Ltd.
英文描述: 64 MB Unbuffered SDRAM DIMM(64MB 未緩沖同步DRAM DIMM)
中文描述: 64 MB的無(wú)緩沖SDRAM的內(nèi)存(64MB的未緩沖同步的DRAM內(nèi)存)
文件頁(yè)數(shù): 25/64頁(yè)
文件大?。?/td> 2741K
代理商: HB52E169EN
HB52E88EM-F, HB52E89EM-F, HB52E168EN-F, HB52E169EN-F
25
Relationship Between Frequency and Minimum Latency
Notes: 1. I
RCD
to I
RRD
are recommended value.
Parameter
Frequency (MHz)
t
CK
(ns)
Active command to column command (same bank) I
RCD
Active command to active command (same bank)
HITACHI-
Symbol
PC100
Symbol
HB52E88EM/
89EM/
168EN/169EN
-A6F/B6F
100
10
2
7
Notes
1
= [I
RAS
+ I
RP
]
1
1
I
RC
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge command
(same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
I
RAS
5
I
RP
2
1
I
DPL
Tdpl
2
1
I
RRD
2
1
I
SREX
I
APW
Tsrx
Tdal
1
4
2
= [I
DPL
+ I
RP
]
I
SEC
7
= [I
RC
]
3
Precharge command to high impedance
(CE latency = 2)
(CE latency = 3)
Last data out to active command (auto precharge)
(same bank)
Last data out to precharge (early precharge)
(CE latency = 2)
(CE latency = 3)
Column command to column command
Write command to data in latency
DQMB to data in
DQMB to data out
CKE to CK disable
Register set to active command
S to command disable
Power down exit to command input
Burst stop to output valid data hold
(CE latency = 2)
(CE latency = 3)
Burst stop to output high impedance
(CE latency = 2)
(CE latency = 3)
Burst stop to write data ignore
I
HZP
I
HZP
I
APR
Troh
Troh
2
3
1
I
EP
I
EP
I
CCD
I
WCD
I
DID
I
DOD
I
CLE
I
RSA
I
CDD
I
PEC
–1
–2
1
0
0
2
1
1
0
1
Tccd
Tdwd
Tdqm
Tdqz
Tcke
Tmrd
I
BSR
I
BSR
1
2
I
BSH
I
BSH
I
BSW
2
3
0
相關(guān)PDF資料
PDF描述
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