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參數(shù)資料
| 型號： | GT28F320D18B120 |
| 英文描述： | x16 Flash EEPROM |
| 中文描述： | x16閃存EEPROM |
| 文件頁數(shù)： | 7/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | GT28F320D18B120 |
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28F320D18
Product Preview
3
Table 1. Ball Descriptions
Sym
Type
Name and Function
A
0
–A
20
I
ADDRESS INPUTS:
for memory addresses.
32-Mbit: A
0-20
DQ
0
–DQ
15
I/O
DATA INPUT/OUTPUTS:
Inputs data and commands during write cycles, outputs data during memory,
status register, and configuration code reads. Data balls float when the chip or outputs are deselected.
Data is internally latched during writes.
CLK
I
CLOCK:
Synchronizes the memory to the system bus operating frequency in synchronous-read
configuration. The first rising (or falling if RCR.6 is 0) CLK edge latches the address when ADV# is
active or upon a rising ADV# edge. This is used only for synchronous operation.
ADV#
I
ADDRESS VALID:
ADV# indicates valid address presence on address inputs. Addresses are latched
on ADV#’s rising edge during read and write operations. This is used only for synchronous operation.
RST#
I
RESET:
When low, RST# resets internal automation and inhibits write operations. This provides data
protection during power transitions. RST#-high enables normal operation. Exit from reset places the
device in asynchronous read array mode.
OE#
I
OUTPUT ENABLE:
OE# gates the device’s outputs during a read cycle.
WE#
I
WRITE ENABLE:
WE# controls writes to the CUI and array. Addresses and data are latched on the
WE# pulse’s rising edge.
WP#
I
WRITE PROTECT:
Controls the lock-down function of the flexible Locking feature.
When WP# is a logic low, the lock-down mechanism is enabled
and blocks marked lock-down
cannot be unlocked through software.
When WP# is logic high, the lock-down mechanism is disabled
and blocks previously locked-down
are now locked and can be unlocked and locked through software. After WP# goes low, any blocks
previously marked lock-down revert to that state.
See
Section 3.2
for details on block locking.
WAIT#
O
WAIT:
Feeds back data valid status in synchronous burst mode while OE# is asserted. When high
during a burst sequence, data is valid. WAIT#-low indicates invalid data. WAIT# is pulled high by an
internal register. Several component WAIT# signals can be tied together to drive one system WAIT
signal. WAIT# is used only for synchronous operation. It also works during a 4, 8-word burst mode if the
No-Wrap bit (RCR.3) is set to 1.
V
PP
Pwr
BLOCK ERASE AND PROGRAM POWER:
A valid voltage on this pin allows block erase or data
programming. Memory contents cannot be altered when V
PP
≤
V
PPLK
. Block erase and program at
invalid V
PP
voltages should not be attempted.
11.4 V–12.6 V V
PP
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for
2500 cycles.
Maximum
V
PP
can be connected to 12 V for 80 hours maximum total. Use of this pin at
12 V beyond these limits may reduce block cycling capability or cause permanent damage.
V
CC
Pwr
DEVICE POWER SUPPLY (1.65 V
–
1.95 V):
Flash memory writes are inhibited at V
CC
≤
V
LKO
. Device
operations at invalid V
CC
voltages should not be attempted.
V
CCQ
Pwr
OUTPUT POWER SUPPLY (1.65 V
–
1.95 V):
Enables all outputs to be driven at 1.65 V to 1.95 V. This
input may be tied directly to V
CC
.
V
SSQ
Pwr
I/O GROUND:
Do not float any ground pins.
V
SS
Pwr
GROUND:
Do not float any ground pins.
NC
NO CONNECT:
Lead is not internally connected; it may be driven or floated.
DU
DON’T USE:
Do not use this pin. This pin should not be connected to any power supplies, signals or
other pins.
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| GT28F320S3-100 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile⑩ MEMORY FAMILY |
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