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| 型號： | GT28F320D18B120 |
| 英文描述： | x16 Flash EEPROM |
| 中文描述： | x16閃存EEPROM |
| 文件頁數(shù)： | 53/83頁 |
| 文件大?。?/td> | 836K |
| 代理商： | GT28F320D18B120 |
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28F320D18
Product Preview
49
WP#: on the Fast Boot Block and other Intel Flash memory families, this pin was the only way
of locking and unlocking lockable blocks. On 1.8 Volt Dual-Plane Flash memory, locking and
unlocking lockable blocks is possible through both hardware and software. Initially, upon
reset, all blocks are locked and cannot be programmed or erased regardless of the value of
WP#. In order to write to or erase a block, it must first be unlocked. This is done through
software. An unlocked block can be programmed or erased regardless of the value of WP#.
Only when a block is marked “l(fā)ock-down” does the WP# pin have an effect on memory. In
order to program/erase a locked-down block, the WP# pin must be high, and the block must
then be unlocked. The block may then be programmed or erased as long as WP# is high. When
WP# goes low, the block reverts to lock-down and can no longer be programmed or erased.
The only way to get the block out of lock-down mode is to reset the device. If WP# is not used,
it should be tied high. This will insure that blocks can be locked and unlocked through
software, even after setting the lock-down bit. With WP# tied low, blocks can still be locked
and unlocked through software, but if a block is locked down, it will remain in a lock-down
state, and cannot be programmed or erased until the flash memory is reset.
WE# / OE#: Processors that have separate pins to signal reads and writes can, in most cases,
connect directly to these pins on the flash memory component. Processors that have a single
pin which determines a read or a write can use this signal directly as either WE# or OE#,
depending on what the low value means on that pin. The other input signal will then need to be
generated via external logic to ensure that it goes low and high at the right times.
RST# on the flash can be connected to the reset signal to the processor provided that the time
from deserting reset to the processor’s first memory request is longer than the time required of
the flash. The maximum delay from deasserting reset to valid data for 1.8 Volt Dual-Plane
Flash memory is 150 ns. If the processor takes less time than that and requires memory before
the flash component is ready, the data will be invalid. If the processor takes longer than the
flash to reset, there is no problem. If this pin is kept low on power-up it will prevent possible
spurious writes. If V
PP
ramps up before V
CC
or V
CC
drops before V
PP
, random noise on the
data pins can possibly enter a program command (40H) with CE# and WE# low and OE# high.
With RST# low it will prevent this spurious write.
Most processors will expect data during read cycles much sooner than the flash memory
component can provide it. For this reason the processor needs to be able to pause and wait for
the flash memory. This can be done by programming the processor to generate a set number of
wait states, if possible. If the processor is unable to internally generate wait-states, an input pin
to the processor tells it when to pause and wait for valid data from the flash memory. This pin
can then also be used as an input from the flash memory’s WAIT# signal during continuous
reads or during 4- or 8-word reads in non-wrap mode (RCR.3 = 1)
7.3.6
Using WAIT# in Burst Mode
The 1.8 Volt Dual-Plane Flash memory supports 4-word, 8-word, and continuous burst lengths. In
continuous burst length, or in 4-word or 8-word burst lengths with no-wrap (RCR.3 = 1), an output
pin, WAIT#, is provided to simplify CPU to memory communication. The WAIT# informs the
system to when data is valid.
WAIT# = Logic ’1’ means Valid Data
WAIT# = Logic ’0’ means Invalid Data
When operating in the continuous burst mode, or during 4 or 8-word reads in non-wrap mode
(RCR.3 = 1), the flash memory may incur an output delay when the burst sequence crosses the first
16-word boundary. The starting address dictates whether or not a delay will occur. If the starting
address is aligned to a four-word boundary, the delay will not be seen. If the starting address is the
end of a four-word boundary, the output delay will be equal to the frequency configuration setting;
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GT28F320S3-100 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile⑩ MEMORY FAMILY |
| GT28F320S3-120 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:WORD-WIDE FlashFile MEMORY FAMILY |
| GT28F320W18BC60 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel? Wireless Flash Memory |
| GT28F320W18BC80 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel? Wireless Flash Memory |
| GT28F320W18BD60 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel㈢ Wireless Flash Memory |
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