參數(shù)資料
型號(hào)： GT28F320D18B120
英文描述： x16 Flash EEPROM
中文描述： x16閃存EEPROM
文件頁數(shù)： 21/83頁
文件大小： 836K
代理商： GT28F320D18B120
28F320D18
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17
4.4
Read Status Register Command
A partition’s status register can be read at any time by writing the Read Status Register command
to the partition’s CUI. Subsequent single transfer read operations to that partition will output its
status register data until another valid command is written. This operation does not affect the other
partition’s mode. See
Table 7
for status register bit definitions.
4.5
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be cleared
by issuing the Clear Status Register command. These bits indicate various error conditions. By
allowing system software to reset these bits, several operations may be performed (such as
cumulatively erasing or writing several bytes in sequence). The status register may be polled to
determine if a problem occurred during the sequence. The Clear Status Register command
functions independently of the applied V
PP
voltage. After executing this command, the device
returns to read array mode. The Clear Status Register command clears only the status register of the
addressed partition.
Table 7. Status Register Definition
WSMS
ESS
ES
PS
VPPS
PSS
DPS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check SR.7 to determine block erase or program completion.
SR.6–0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
When an Erase Suspend command is issued, the WSM halts
execution and sets both SR.7 and SR.6 to “1.” SR.6 remains set
until an Erase Resume command is written to the CUI.
SR.5 = ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
If both SR.5 and SR.4 are “1”s after a block erase or lock block
attempt, an improper command sequence was entered.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Program
0 = Successful Program
SR.3 = V
PP
STATUS (VPPS)
1 = V
PP
Low Detect, Operation Abort
0 = V
PP
OK
SR.3 does not provide a continuous V
feedback. The WSM
interrogates and indicates the V
level only after a block erase
or program operation. SR.3 is not guaranteed to report accurate
feedback when V
PP
≠
V
PP1/2
or V
PPLK
.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When a Program Suspend command is issued, the WSM halts
execution and sets both SR.7 and SR.2 to “1.” SR.2 remains set
until a Program Resume command is written to the CUI.
SR.1 = DEVICE PROTECT STATUS (DPS)
1 = Block Erase or Program Attempted on a Locked
Block, Operation Abort
0 = Unlocked
If a block erase or program operation is attempted to a locked
block, SR.1 is set by the WSM and aborts the operation if WP# =
V
IL
.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
SR.0 is reserved for future use and should be masked out when
polling the status register.
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