參數(shù)資料
型號(hào): GT28F320D18B120
英文描述: x16 Flash EEPROM
中文描述: x16閃存EEPROM
文件頁數(shù): 28/83頁
文件大?。?/td> 836K
代理商: GT28F320D18B120
28F320D18
24
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4.10.7
Burst Wrap
The burst wrap bit determines whether 4- or 8-word burst-accesses wrap within the burst-length
boundary or whether they cross word-length boundaries to perform linear accesses. No-wrap mode
(RCR.3 = 1) enables WAIT# to hold off the system processor, as it does in the continuous burst
mode. In the no-wrap mode, the device operates similar to continuous linear burst mode but
consumes less power during 4- and 8-word bursts.
For example, if RCR.3 = 0 (wrap mode) and RCR.2-0 = 001 (4-word burst length), then possible
linear burst sequences are 0-1-2-3, 1-2-3-0, 2-3-0-1, and 3-0-1-2.
If RCR.3 = 1 (no-wrap mode) and RCR.2-0 = 001 (4-word burst length), then possible linear burst
sequences are 0-1-2-3, 1-2-3-4, 2-3-4-5, and 3-4-5-6. RCR.3 = 1 not only enables limited non-
aligned sequential burst, but also reduces power by minimizing the number of internal read
operations.
The above 4-word burst sequences can also be achieved by setting RCR.2-0 bits for continuous
linear burst mode (111). However, significantly more power may be consumed. The 1-2-3-4
sequence, for example, will consume power during the initial access, again during the internal
pipeline lookup as the processor reads word 2, and possibly again, depending on system timing,
near the end of the sequence as the device pipelines the next 4-word sequence. RCR.3 = 1 mode
reduces this excess power consumption.
4.10.8
Burst Length
The burst length is the number of words that the device will output. The device supports burst
lengths of four and eight words. It also supports a continuous burst mode. In continuous burst
mode, the device will linearly output data until the internal burst counter reaches the end of the
device’s burst-able address space or a partition boundary. Bits RCR.2–0 in the read configuration
register set the burst length.
4.10.8.1
Continuous Burst Length
When operating in the continuous burst mode or 4-, 8-word burst with burst wrap bit set (RCR.3 =
1), the flash memory may incur an output delay when the burst sequence crosses the first sixteen
word boundary. The starting address dictates whether or not a delay will occur. If the starting
address is aligned to a four word boundary, the delay will not be seen. If the starting address is the
end of a four word boundary, the output delay will be equal to the frequency configuration setting;
this is the worst case delay. The delay will only take place once during a continuous burst access. If
the burst sequence never crosses a sixteen word boundary, the delay will never happen. The flash
memory uses the WAIT# output pin in the continuous burst configuration to inform the system if
this output delay occurs.
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