參數(shù)資料
型號(hào)： EVAL-ADUC824QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 55/68頁(yè)
文件大?。?/td> 0K
描述： KIT DEV QUICK START ADUC824
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC824
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
REV. B
ADuC824
–59–
Timer 1 Generated Baud Rates
When Timer 1 is used as the baud rate generator, the baud rates
in Modes 1 and 3 are determined by the Timer 1 overflow rate and
the value of SMOD as follows:
Modes 1 and 3 Baud Rate = (2
SMOD/32)
× (Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application. The
Timer itself can be configured for either timer or counter opera-
tion, and in any of its three running modes. In the most typical
application, it is configured for timer operation, in the autoreload
mode (high nibble of TMOD = 0100Binary). In that case, the baud
rate is given by the formula:
Modes 1 and 3 Baud Rate =
(2
SMOD/32)
× (Core Clock/(12 × [256-TH1]))
A very low baud rate can also be achieved with Timer 1 by leaving
the Timer 1 interrupt enabled, and configuring the timer to run
as a 16-bit timer (high nibble of TMOD = 0100Binary), and using
the Timer 1 interrupt to do a 16-bit software reload. Table XXVIII
below, shows some commonly-used baud rates and how they
might be calculated from a core clock frequency of 1.5728 MHz
and 12.58 MHz. Generally speaking, a 5% error is tolerable
using asynchronous (start/stop) communications.
Table XXVIII. Commonly Used Baud Rates, Timer 1
Ideal
Core
SMOD
TH1-Reload
Actual
%
Baud
CLK
Value
Baud
Error
9600
12.58
1
–7 (F9h)
9362
2.5
2400
12.58
1
–27 (E5h)
2427
1.1
1200
12.58
1
–55 (C9h)
1192
0.7
1200
1.57
1
–7 (F9h)
1170
2.5
Timer 2 Generated Baud Rates
Baud rates can also be generated using Timer 2. Using Timer 2 is
similar to using Timer 1 in that the timer must overflow 16 times
before a bit is transmitted/received. Because Timer 2 has a 16-bit
autoreload mode a wider range of baud rates is possible using
Timer 2.
Modes 1 and 3 Baud Rate = (1/16)
× (Timer 2 Overflow Rate)
Therefore, when Timer 2 is used to generate baud rates, the timer
increments every two clock cycles and not every core machine cycle
as before. Hence, it increments six times faster than Timer 1, and
therefore baud rates six times faster are possible. Because Timer 2
has 16-bit autoreload capability, very low baud rates are still possible.
Timer 2 is selected as the baud rate generator by setting the TCLK
and/or RCLK in T2CON. The baud rates for transmit and receive
can be simultaneously different. Setting RCLK and/or TCLK puts
Timer 2 into its baud rate generator mode as shown in Figure 42.
In this case, the baud rate is given by the formula:
Modes 1 and 3 Baud Rate
= (Core Clk)/(32
× [65536 – (RCAP2H, RCAP2L)])
Table XXIX shows some commonly used baud rates and how they
might be calculated from a core clock frequency of 1.5728 MHz
and 12.5829 MHz.
Table XXIX. Commonly Used Baud Rates, Timer 2
Ideal
Core
RCAP2H
RCAP2L
Actual
%
Baud
CLK
Value
Baud
Error
19200
12.58
–1 (FFh)
–20 (ECh)
19661
2.4
9600
12.58
–1 (FFh)
–41 (D7h)
9591
0.1
2400
12.58
–1 (FFh)
–164 (5Ch)
2398
0.1
1200
12.58
–2 (FEh)
–72 (B8h)
1199
0.1
9600
1.57
–1 (FFh)
–5 (FBh)
9830
2.4
2400
1.57
–1 (FFh)
–20 (ECh)
2458
2.4
1200
1.57
–1 (FFh)
–41 (D7h)
1199
0.1
CORE
CLK*
2
T2
PIN
TR2
CONTROL
TL2
(8-BITS)
TH2
(8-BITS)
RELOAD
EXEN2
CONTROL
T2EX
PIN
RCAP2L
RCAP2H
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12.
TIMER 2
OVERFLOW
2
16
RCLK
TCLK
RX
CLOCK
TX
CLOCK
0
1
0
SMOD
TIMER 1
OVERFLOW
TRANSITION
DETECTOR
EXF
2
TIMER 2
INTERRUPT
NOTE AVAILABILITY OF ADDITIONAL
EXTERNAL INTERRUPT
C/
T2 = 0
C/
T2 = 1
*THE CORE CLOCK IS THE OUTPUT OF THE PLL AS DESCRIBED ON PAGE 42.
Figure 42. Timer 2, UART Baud Rates
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