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| 型號： | EVAL-ADUC824QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV QUICK START ADUC824 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC824 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
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REV. B
ADuC824
–42–
ON-CHIP PLL
The ADuC824 is intended for use with a 32.768 kHz watch crys-
tal. A PLL locks onto a multiple (384) of this to provide a stable
12.582912 MHz clock for the system. The core can operate at
this frequency or at binary submultiples of it to allow power
saving in cases where maximum core performance is not
required. The default core clock is the PLL clock divided by
8 or 1.572864 MHz. The ADC clocks are also derived from the
PLL clock, with the modulator rate being the same as the crystal
oscillator frequency. The above choice of frequencies ensures
that the modulators and the core will be synchronous, regardless
of the core clock rate. The PLL control register is PLLCON.
PLLCON
PLL Control Register
SFR Address
D7H
Power-On Default Value
03H
Bit Addressable
No
Table XV. PLLCON SFR Bit Designations
Bit
Name
Description
7
OSC_PD
Oscillator Power-down Bit
Set by user to halt the 32 kHz oscillator in power-down mode.
Cleared by user to enable the 32 kHz oscillator in power-down mode.
This feature allows the TIC to continue counting even in power-down mode.
6
LOCK
PLL Lock Bit
This is a read only bit.
Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the
external crystal becomes subsequently disconnected the PLL will rail and the core will halt.
Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.
This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode,
the PLL output can be 12.58 MHz
± 20%.
5
—
Reserved for future use; should be written with ‘0.’
4
LTEA
Reading this bit returns the state of the external
EA pin latched at reset or power-on.
3
FINT
Fast Interrupt Response Bit
Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
regardless of the configuration of the CD2–0 bits (see below). Once user code has returned from an
interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits.
Cleared by user to disable the fast interrupt response feature.
2
CD2
CPU (Core Clock) Divider Bits
1
CD1
This number determines the frequency at which the microcontroller core will operate.
0
CD0
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
12.582912
0
1
6.291456
0
1
0
3.145728
0
1
1.572864 (Default Core Clock Frequency)
1
0
0.786432
1
0
1
0.393216
1
0
0.196608
1
0.098304
OSC_PD
LOCK
—
LTEA
FINT
CD2
CD1
CD0
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