參數(shù)資料
型號(hào)： EVAL-ADUC824QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/68頁(yè)
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描述： KIT DEV QUICK START ADUC824
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC824
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
REV. B
ADuC824
–25–
SFR INTERFACE TO THE PRIMARY AND AUXILIARY
ADCS
Both ADCs are controlled and configured via a number of SFRs
that are mentioned here and described in more detail in the
following pages.
ADCSTAT:
ADC Status Register. Holds general status of
the Primary and Auxiliary ADCs.
ADCMODE: ADC Mode Register. Controls general modes
of operation for Primary and Auxiliary ADCs.
ADC0CON:
Primary ADC Control Register. Controls
specific configuration of Primary ADC.
ADC1CON:
Auxiliary ADC Control Register. Controls
specific configuration of Auxiliary ADC.
SF:
Sinc Filter Register. Configures the decimation
factor for the Sinc3 filter and thus the Primary
and Auxiliary ADC update rates.
ICON:
Current Source Control Register. Allows user
control of the various on-chip current source
options.
ADC0L/M/H: Primary ADC 24-bit conversion result held in
these three 8-bit registers.
ADC1L/H:
Auxiliary ADC 16-bit conversion result held
in these two 8-bit registers.
OF0L/M/H:
Primary ADC 24-bit Offset Calibration Coefficient
held in these three 8-bit registers.
OF1L/H:
Auxiliary ADC 16-bit Offset Calibration Coefficient
held in these two 8-bit registers.
GN0L/M/H:
Primary ADC 24-bit Gain Calibration Coefficient
held in these three 8-bit registers.
GN1L/H:
Auxiliary ADC 16-bit Gain Calibration Coefficient
held in these two 8-bit registers.
ADCSTAT—(ADC Status Register)
This SFR reflects the status of both ADCs including data ready, calibration and various (ADC-related) error and warning conditions
including reference detect and conversion overflow/underflow flags.
SFR Address
D8H
Power-On Default Value
00H
Bit Addressable
Yes
0
Y
D
R1
Y
D
RL
A
CF
E
R
X
O
N0
R
E1
R
E—
—
Table III. ADCSTAT SFR Bit Designations
Bit
Name
Description
7
RDY0
Ready Bit for Primary ADC
Set by hardware on completion of ADC conversion or calibration cycle.
Cleared directly by the user or indirectly by write to the mode bits to start another Primary
ADC conversion or calibration. The Primary ADC is inhibited from writing further results to its
data or calibration registers until the RDY0 bit is cleared.
6
RDY1
Ready Bit for Auxiliary ADC
Same definition as RDY0 referred to the Auxiliary ADC.
5
CAL
Calibration Status Bit
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
4
NOXREF
No External Reference Bit (only active if Primary or Auxiliary ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a
specified threshold. When Set conversion results are clamped to all ones,if using ext. reference.
Cleared to indicate valid VREF.
3
ERR0
Primary ADC Error Bit
Set by hardware to indicate that the result written to the Primary ADC data registers has
been clamped to all zeros or all ones. After a calibration this bit also flags error conditions that
caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
2
ERR1
Auxiliary ADC Error Bit
Same definition as ERR0 referred to the Auxiliary ADC.
1
—
Reserved for Future Use
0
—
Reserved for Future Use
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