參數(shù)資料
型號： DSPB56366AG120
廠商： Freescale Semiconductor
文件頁數(shù)： 100/110頁
文件大?。?/td> 0K
描述： IC DSP 24BIT AUD 120MHZ 144-LQFP
產(chǎn)品變化通告： Product Discontinuation 24/Feb/2012
標(biāo)準(zhǔn)包裝： 60
系列： DSP56K/Symphony
類型： 音頻處理器
接口： 主機(jī)接口，I²C，SAI，SPI
時鐘速率： 120MHz
非易失內(nèi)存： ROM（240 kB）
芯片上RAM： 69kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 110°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
包裝： 托盤
DSP56366 Technical Data, Rev. 3.1
Freescale Semiconductor
2-5
2.5.1
External Address Bus
2.5.2
External Data Bus
2.5.3
External Bus Control
Table 2-5 External Address Bus Signals
Signal
Name
Type
State
during
Reset
Signal Description
A0–A17
Output
Tri-stated
Address Bus—When the DSP is the bus master, A0–A17 are active-high outputs
that specify the address for external program and data memory accesses.
Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not
change state when external memory spaces are not being accessed.
Table 2-6 External Data Bus Signals
Signal
Name
Type
State
during
Reset
Signal Description
D0–D23
Input/Output
Tri-stated
Data Bus—When the DSP is the bus master, D0–D23 are active-high,
bidirectional input/outputs that provide the bidirectional data bus for external
program and data memory accesses. Otherwise, D0–D23 are tri-stated.
Table 2-7 External Bus Control Signals
Signal Name
Type
State during
Reset
Signal Description
AA0–AA2/
RAS0–RAS2
Output
Tri-stated
Address Attribute or Row Address Strobe—When defined as AA, these
signals can be used as chip selects or additional address lines. When defined
as RAS, these signals can be used as RAS for DRAM interface. These signals
are tri-statable outputs with programmable polarity.
CAS
Output
Tri-stated
Column Address Strobe— When the DSP is the bus master, CAS is an
active-low output used by DRAM to strobe the column address. Otherwise, if the
bus mastership enable (BME) bit in the DRAM control register is cleared, the
signal is tri-stated.
RD
Output
Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low output
that is asserted to read external memory on the data bus (D0-D23). Otherwise,
RD is tri-stated.
WR
Output
Tri-stated
Write Enable—When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D0-D23). Otherwise,
WR is tri-stated.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSPB56366PV120 制造商:Motorola Inc 功能描述: 制造商:Freescale Semiconductor 功能描述:IC 制造商:MOTOROLA 功能描述:
DSPB56367AG150 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 150Mhz/150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB56367PV150 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 150Mhz/ 150MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSPB5636AG120 制造商:Freescale Semiconductor 功能描述:
DSPB56371AF150 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 150 MHZ VERSION DSPB371 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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