HDBDR High from Read Data Strobe Deas" />
參數(shù)資料
型號： DSP56301VF100
廠商： Freescale Semiconductor
文件頁數(shù)： 83/124頁
文件大?。?/td> 0K
描述： IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告： DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝： 60
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 252-BGA
供應(yīng)商設(shè)備封裝： 252-MAPBGA（21x21）
包裝： 托盤
AC Electrical Characteristics
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
2-35
345
HDBDR High from Read Data Strobe Deassertion3
—
22.2
—
19.6
ns
346
HRST Assertion to Host Port Pins High Impedance2
—
22.2
—
19.6
ns
Notes:
1.
The Data Strobe is HRD or HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
2.
HTA, HDRQ, and HRST may be programmed as active-high or active-low. In the example timing diagrams, HDRQ and HRST
are shown as active-high and HTA is shown as active low.
3.
The Read Data Strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
4.
The Write Data Strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
5.
HTA requires an external pull-down resistor if programmed as active high (HTAP = 0); or an external pull-up resistor if
programmed as active low (HTAP = 1). The resistor value should be consistent with the DC specifications.
6.
HIRQ requires an external pull-up resistor if programmed as open drain (HIRD = 0). The resistor value should be consistent
with the DC specifications.
7.
“LT” is the value of the latency timer register (CLAT) as programmed by the user during self configuration.
LT
≥ 1.
8.
Values are valid for VCC = 3.3 ± 0.3V
Table 2-19.
Universal Bus Mode, Synchronous Port A Type Host Timing
No.
Characteristic
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
300
Access Cycle Time
3
× TC
37.5
—
30.0
—
ns
301
HA[10–0], HAEN Setup to Data Strobe Assertion1
5.8
—
4.6
—
ns
302
HA[10–0], HAEN Valid Hold from Data Strobe Deassertion1
0.0
—
0.0
—
ns
305
Data Strobe Deasserted Width1
4.1
—
3.3
—
ns
307
HBS Asserted Pulse Width
2.5
—
2.0
—
ns
308
HBS Assertion to Data Strobe Assertion1
80 MHz: TC 4.9
100 MHz: TC 4.0
—7.6
—6.0
ns
309
HBS Assertion to Data Strobe Deassertion1
80 MHz: 2.5
× TC + 2.9
100 MHz: 2.5
× TC + 2.3
34.1
—
27.3
—
ns
310
HBS Deassertion to Data Strobe Deassertion1
80 MHz: 1.5
× TC + 3.3
100 MHz: 1.5
× TC + 2.6
22.1
—
17.6
—
ns
312
Data Out Active from Read Data Strobe Assertion3
1.7
—
1.3
—
ns
313
Data Out Valid from Read Data Strobe Assertion
(No Wait States Inserted—HTA Asserted)3
—
18.9
—
16.9
ns
314
Data Out Valid Hold from Read Data Strobe Deassertion3
1.7
—
1.3
—
ns
315
Data Out High Impedance from Read Data Strobe Deassertion3
—
12.0
—
9.6
ns
316
Data In Valid Setup to Write Data Strobe Deassertion4
8.3
—
6.6
—
ns
317
Data In Valid Hold from Write Data Strobe Deassertion4
0.0
—
0.0
—
ns
324
HTA Assertion to Data Strobe Deassertion1,2
0.0
—
0.0
—
ns
325
HTA High Impedance from Data Strobe Deassertion1,2
—
15.3
—
12.2
ns
326
HIRQ Asserted Pulse Width (HIRH = 0, HIRD = 1)
(LT + 1)
× TC 6.07
6.5
—
4.0
—
ns
327
Data Strobe Deasserted Hold from HIRQ Deassertion
(HIRH = 0)1
0.0
—
0.0
—
ns
328
HIRQ Asserted Hold from Data Strobe Assertion (HIRH = 1)1
1.5
× TC
18.8
—
15.0
—
ns
329
HIRQ Deassertion from Data Strobe Assertion
(HIRH = 1, HIRD = 1)1
80 MHz: 2.5
× TC + 24.7
100 MHz: 2.5
× TC + 21.5
—
55.9
—
46.5
ns
Table 2-18.
Universal Bus Mode Timing Parameters (Continued)
No.
Characteristic
Expression
80 MHz
100 MHz
Unit
Min
Max
Min
Max
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