參數(shù)資料
型號: DSP56301VF100
廠商: Freescale Semiconductor
文件頁數(shù): 21/124頁
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告: DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝: 60
系列: DSP563xx
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 100MHz
非易失內(nèi)存: ROM(9 kB)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 252-BGA
供應(yīng)商設(shè)備封裝: 252-MAPBGA(21x21)
包裝: 托盤
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
A-11
M_D5L EQU $C00000; DMA5 Interrupt priority Level Mask
M_D5L0 EQU 22
; DMA5 Interrupt Priority Level (low)
M_D5L1 EQU 23
; DMA5 Interrupt Priority Level (high)
;
Interrupt Priority Register Peripheral (IPRP)
M_HPL EQU $3
; Host Interrupt Priority Level Mask
M_HPL0 EQU 0
; Host Interrupt Priority Level (low)
M_HPL1 EQU 1
; Host Interrupt Priority Level (high)
M_S0L EQU $C
; SSI0 Interrupt Priority Level Mask
M_S0L0 EQU 2
; SSI0 Interrupt Priority Level (low)
M_S0L1 EQU 3
; SSI0 Interrupt Priority Level (high)
M_S1L EQU $30
; SSI1 Interrupt Priority Level Mask
M_S1L0 EQU 4
; SSI1 Interrupt Priority Level (low)
M_S1L1 EQU 5
; SSI1 Interrupt Priority Level (high)
M_SCL EQU $C0
; SCI
Interrupt Priority Level
Mask
M_SCL0 EQU 6
; SCI
Interrupt Priority Level
(low)
M_SCL1 EQU 7
; SCI
Interrupt Priority Level
(high)
M_T0L EQU $300
; TIMER Interrupt Priority Level Mask
M_T0L0 EQU 8
; TIMER Interrupt Priority Level (low)
M_T0L1 EQU 9
; TIMER Interrupt Priority Level (high)
;------------------------------------------------------------------------
;
EQUATES for TIMER
;
;------------------------------------------------------------------------
;
Register Addresses Of TIMER0
M_TCSR0 EQU $FFFF8F; TIMER0 Control/Status Register
M_TLR0 EQU $FFFF8E; TIMER0 Load Reg
M_TCPR0 EQU $FFFF8D; TIMER0 Compare Register
M_TCR0 EQU $FFFF8C ; TIMER0 Count Register
;
Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B; TIMER1 Control/Status Register
M_TLR1 EQU $FFFF8A; TIMER1 Load Reg
M_TCPR1 EQU $FFFF89; TIMER1 Compare Register
M_TCR1 EQU $FFFF88; TIMER1 Count Register
;
Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87; TIMER2 Control/Status Register
M_TLR2 EQU $FFFF8; TIMER2 Load Reg
M_TCPR2 EQU $FFFF85; TIMER2 Compare Register
M_TCR2 EQU $FFFF84 ; TIMER2 Count Register
M_TPLR EQU $FFFF83 ; TIMER Prescaler Load Register
M_TPCR EQU $FFFF82 ; TIMER Prescalar Count Register
;
Timer Control/Status Register Bit Flags
M_TE EQU 0
; Timer Enable
M_TOIE EQU 1
; Timer Overflow Interrupt Enable
M_TCIE EQU 2
; Timer Compare Interrupt Enable
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