參數(shù)資料
型號: DSP56301VF100
廠商: Freescale Semiconductor
文件頁數(shù): 32/124頁
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
產品變化通告: DSP56301 Discontinuation 12/Nov/2009
標準包裝: 60
系列: DSP563xx
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 100MHz
非易失內存: ROM(9 kB)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 252-BGA
供應商設備封裝: 252-MAPBGA(21x21)
包裝: 托盤
Host Interface (HI32)
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-11
1.7.2
Host Port Configuration
HI32 signal functions vary according to the programmed configuration of the interface as determined by the 24-bit
DSP Control Register (DCTR). Refer to the DSP56301 User’s Manual for details on HI32 configuration registers.
Asynchronous write to host
vector
Change the Host Vector (HV) register only when the Host Command bit (HC) is clear. This practice
guarantees that the DSP interrupt control logic receives a stable vector.
Table 1-11.
Host Interface
Signal Name
Type
State During
Reset
Signal Description
HAD[0–7]
HA[3–10]
PB[0–7]
Input/Output
Input
Input or Output
Tri-stated
Host Address/Data 0–7
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 0–7 of the Address/Data bus.
Host Address 3–10
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, these signals are lines 3–10 of the Address bus.
Port B 0–7
When the HI32 is configured as GPIO through the DCTR, these signals are
individually programmed through the HI32 Data Direction Register (DIRH).
These inputs are 5 V tolerant.
HAD[8–15]
HD[0–7]
PB[8–15]
Input/Output
Input or Output
Tri-stated
Host Address/Data 8–15
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 8–15 of the Address/Data bus.
Host Data 0–7
When HI32 is programmed to interface with a universal non-PCI bus and the
HI function is selected, these signals are lines 0–7 of the Data bus.
Port B 8–15
When the HI32 is configured as GPIO through the DCTR, these signals are
individually programmed through the HI32 DIRH.
These inputs are 5 V tolerant.
HC[0–3]/
HBE[0–3]
HA[0–2]
PB[16–19]
Input/Output
Input
Input or Output
Tri-stated
Command 0–3/Byte Enable 0–3
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 0–7 of the Address/Data bus.
Host Address 0–2
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, these signals are lines 0–2 of the Address bus.
The fourth signal in this set should connect to a pull-up resistor or directly to
VCC when a non-PCI bus is used.
Port B 16–19
When the HI32 is configured as GPIO through the DCTR, these signals are
individually programmed through the HI32 DIRH.
These inputs are 5 V tolerant.
Table 1-10.
Host Port Usage Considerations (Continued)
Action
Description
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